Description

The i.MXxx HAL provides a number of macros to support the encoding of pin multiplexing information and GPIO pin modes into descriptors. This is useful to drivers and other packages that need to configure and use different lines for different devices. Because there is not a simple correspondence between pin multiplexing information and GPIO bank and pin identities, these two things are treated separately.

Pin Multiplexing

There is no systematic relationship between the various registers that control the properties of a single io pin. So all the information needed to identify and configure a pin is encoded into a 64 bit descriptor. To define a new pin descriptor it is necessary to consult the appropriate processor reference manual for the register offsets and valid settings. A pin multiplexing descriptor is represented by the hal_imx_pin and is created with CYGHWR_HAL_IMX_PINMUX() which takes the following arguments:

The following examples show how this macro may be used:

// UART1 RX line, with 100K Ohm pull down, mux 0
#define CYGHWR_HAL_IMX_UART1_RX \
        CYGHWR_HAL_IMX_PINMUX( 0x368, PUS_100KD, 0x170, MUX_SION(0),     0, NONE   )

// UART4 RX line, 100K Ohm pull down, mux 1, input selection 1
#define CYGHWR_HAL_IMX_UART4_RX \
        CYGHWR_HAL_IMX_PINMUX( 0x3B0, PUS_100KD, 0x1B8, MUX_SION(1), 0x570, SEL(1) )

// GPIO line, floating, mix 5
#define CYGHWR_HAL_IMX_FEC_RESET \
        CYGHWR_HAL_IMX_PINMUX( 0x238,        FLOAT, 0x01C, MUX(5),     0, NONE   )

The macro CYGHWR_HAL_IMX_PINMUX_SET( pin ) sets the pin multiplexing setting according to the descriptor passed in.

GPIO Support

A GPIO descriptor is created with CYGHWR_HAL_IMX_GPIO( bank, bit, mode) which takes the following arguments:

Additionally, the macro CYGHWR_HAL_IMX_GPIO_NONE may be used in place of a pin descriptor and has a value that no valid descriptor can take. It may therefore be used as a placeholder where no GPIO pin is present or to be used.

The following examples show how this macro may be used:

// PHY Reset pin on GPIO4, pin 8, output
#define CYGHWR_HAL_IMX_FEC_RESET_GPIO   CYGHWR_HAL_IMX_GPIO( 4, 8, OUTPUT )

// CSPI 1, chip select 0 on GPIO1, pin 16, output
#define CYGHWR_HAL_IMX_CSPI1_SS0_GPIO   CYGHWR_HAL_IMX_GPIO( 1, 16, OUTPUT )

The remaining macros all take a GPIO pin descriptor as an argument. CYGHWR_HAL_IMX_GPIO_SET configures the pin according to the descriptor and must be called before any other macros. CYGHWR_HAL_IMX_GPIO_OUT sets the output to the value of the least significant bit of the val argument. The val argument of CYGHWR_HAL_IMX_GPIO_IN should be a pointer to an int, which will be set to 0 if the pin input is zero, and 1 otherwise.

There is also support for GPIO interrupts. CYGHWR_HAL_IMX_GPIO_INTCFG( pin, mode ) configures the interrupt mode of the pin. It may be either LOW_LEVEL, HIGH_LEVEL, RISING_EDGE, FALLING_EDGE or EITHER_EDGE to configure the pin, respectively, to interrupt on active-low, active-high, rising edge, falling edge or both rising and falling edges. For example:

// PHY interrupt on GPIO3 pin 19
#define CYGHWR_HAL_IMX_FEC_INTERRUPT_GPIO CYGHWR_HAL_IMX_GPIO( 3, 19, INPUT )

// Configure active-LOW interrupt
CYGHWR_HAL_IMX_GPIO_INTCFG( CYGHWR_HAL_IMX_FEC_INTERRUPT_GPIO, LOW_LEVEL );

The second argument to CYGHWR_HAL_IMX_GPIO_INTSTAT( pin, stat ) must be a pointer to an int, which will be set to 1 if an interrupt has be received on the given pin, and 0 otherwise.

	Note
	GPIO interrupts are currently not decoded into per-pin interrupt vectors, only the shared per-bank vectors are available. If an application needs to get interrupts from more than one pin on a bank, it needs to install a shared ISR and decode the specific pins itself.

The second argument to CYGHWR_HAL_IMX_GPIO_INTMASK( pin, enable ) when set to 1 will enable the relevant GPIO interrupt source for the configured pin, with 0 disabling the source. If required, CYGHWR_HAL_IMX_GPIO_INTCLR( pin ) can be used to explicitly clear the interrupt status for a specific GPIO pin.