| Chapter 106. Configuration | ||
|---|---|---|
 | Part XXIX. STM32 Coherent Connection Bus Driver |  |
Chapter 106. Configuration
This chapter shows how to incorporate the CCB support into an eCos configuration, and how to configure it once included.
106.1. Configuration Overview
The common CCB support is contained in the eCos
package CYGPKG_IO_CCB. However, it depends on the
services of a collection of other packages for complete functionality,
with this CYGPKG_DEVS_CCB_CORTEXM_STM32 package
providing specific I/O functionality.
Normally this package should not need to be manually added, since it will be automatically provided as part of suitable target configurations.
The functionality of this driver package itself relies on some
platform/variant provided configuration. For platforms that require
software control of the transceiver Device Enable (DE) signal for any
of the CCB ports they will need to implement the
feature CYGINT_DEVS_CCB_CORTEXM_STM32_TXCTRL.
106.1.1. Configuring the STM32 CCB driver
CCB use of the underlying STM32 U(S)ART interfaces is only enabled if the serial driver support for the specific hardware interface is disabled.
Common configuration options applicable to all configured U(S)ART interfaces:
- CYGPKG_DEVS_CCB_CORTEXM_STM32_TIMER
-
This option is used to select the STM32 timer block assigned to this
CCB I/O driver. It is used to ensure correct bus operation timing. The
sub-option
CYGNUM_DEVS_CCB_CORTEXM_STM32_TIMER_INTR_PRIis used to configure the relative interrupt priority for the timer handler. - CYGNUM_DEVS_CCB_CORTEXM_STM32_RETRIES
- This option enables support for abandoning a transmission after the configured number of retry attempts. The default of 0 disables the retry limit check, with a colliding transmission being retried infinitely. NOTE: The Coherent OBIS Integrators Guide Part# 11215508 Rev. AB (dated 4/2012) has conflicting descriptions re. transmission. The “Random Delay” section is explicit in stating “… there is no provision for discarding a message after many collisions; message transmission will retry until it succeeds”. This however is counter to the Figure 5-6 “Outbound Message Transmission Flow” diagram, which implements a retry counter and terminates the transmission attempt after a number of retries. This configuration option allows the developer to choose the model required by their application. A value of 0 will disable the retry support and a colliding TX will be retried until it is successful (no collision detected). A non-zero value will be treated as a count of the number of attempts to be made before abandoning the transmission and indicating a TX BUSY error.
- CYGIMP_DEVS_CCB_CORTEXM_STM32_STATISTICS
- This option is normally disabled by default since it has a (minor) memory footprint and performance hit. If enabled then the driver will track counts of packet transfers and errors. This may be useful to client applications to ascertain bus performance and “quality”.
For the following CDL option names
the #
If the underlying platform/variant provides access to a STM32 U(S)ART interface, via
implementing CYGINT_DEVS_CCB_CORTEXM_STM32_UART,
then the following per-interface configuration options are available:
#
-
CYGPKG_DEVS_CCB_CORTEXM_STM32_UART
# - This is the main option to control use of an interface as a CCB port. Access to the options described below are dependant on this option being enabled.
- CYGDAT_DEVS_CCB_CORTEXM_STM32_UART
#_NAME This option specifies the name of the CCB port for the corresponding STM32 U(S)ART. This is the name that an eCos application should use to access this device via cyg_io_lookup(), open(), or similar calls.
![[Note]](pix/note.png)
Note Normally for CCB use the client-application should NOT need to directly interact with this named device driver, since the common
CYGPKG_IO_CCBsupport will automatically access the target platform configured devices declared viaCCB_PORT()definitions.- CYGNUM_DEVS_CCB_CORTEXM_STM32_UART
#_INT_PRI - Interrupt handler priority for U(S)ART events.
- CYGNUM_DEVS_CCB_CORTEXM_STM32_UART
#_TXINTR_PRI - TX DMA interrupt handler priority.
- CYGNUM_DEVS_CCB_CORTEXM_STM32_UART
#_RXINTR_PRI - RX DMA interrupt handler priority.
- CYGHWR_DEVS_CCB_CORTEXM_STM32_UART
#_ONEBIT - This option controls the configuration of the STM32 hardware serial bit sampling. The (default) NOISY selection is suited to off-board interfaces where noise/glitches may occur, but is less tolerant of clock differences. The CLOCK selection is more tolerant of clock deviation between the transmitted and receiver. Use of CLOCK may be more suited to on-board high bitrate connections.
| |  | |
| Chapter 105. STM32 Coherent Connection Bus Driver overview |  | Chapter 107. Debug and Test |
| 2024-12-10 | eCosPro Non-Commercial Public License |