Chapter 199. Platform/Variant HAL

To correctly operate the WWD driver needs to have some platform specific support that identifies the WICED-SDK features needed to support a specific Cypress/Broadcom chipset configuration. This chapter is primarily aimed at developers that need to provide WWD support on platforms without existing WWD support.

Some manifests control the features that are provided by the platform, and may be required depending on the specific WICED module being supported.

Table 199.1. WICED options

WICED_CPU_CLOCK_HZ Provides the eCos run-time clock frequency to the WICED system.
WICED_WIFI_USE_GPIO_FOR_BOOTSTRAP_0 Specifies that a GPIO pin is provided for the BOOTSTRAP_0 startup configuration of the WiFi chip.
WICED_WIFI_USE_GPIO_FOR_BOOTSTRAP_1 Specifies that a GPIO pin is provided for the BOOTSTRAP_1 startup configuration of the WiFi chip.
WICED_WIFI_OOB_IRQ_GPIO_PIN Out-Of-Band (asynchronous) interrupt pin provided.
WICED_USE_WIFI_POWER_PIN WiFi chip power control pin provided.
WICED_USE_WIFI_POWER_PIN_ACTIVE_HIGH Selects active-HIGH polarity for the power control pin, otherwise is active-LOW.
WICED_USE_WIFI_RESET_PIN WiFi chip reset control pin provided.
WICED_USE_WIFI_32K_CLOCK_MCO 32kHz clock provided.

As well as the WICED feature configuration, the platform needs to define the set of hardware features as present on the targetted platform. Only the necessary subset of these will be defined, as dictated by how the WiFi chipset signals are wired on the target platform.

Table 199.2. Hardware manifests

CYGHWR_HAL_STM32_WWD_MCO1 Pin descriptor for clock source.
CYGHWR_HAL_PLF_CLOCK_MCO_32K Platform specific function used to configure the 32kHz clock source.
CYGHWR_HAL_PLF_WWD_PIN_POWER GPIO pin descriptor for power control.
CYGHWR_HAL_PLF_WWD_PIN_RESET GPIO pin descriptor for reset control.
CYGHWR_HAL_PLF_WWD_PIN_32K_CLK Pin descriptor for 32kHz clock source.
CYGHWR_HAL_PLF_WWD_PIN_32K_GPIO GPIO pin descriptor for 32kHz clock source.
CYGHWR_HAL_PLF_WWD_PIN_BOOTSTRAP_0 GPIO pin descriptor for bootstrap 0.
CYGHWR_HAL_PLF_WWD_PIN_BOOTSTRAP_1 GPIO pin descriptor for bootstrap 1.
CYGHWR_HAL_PLF_WWD_PIN_SPI_IRQ GPIO pin descriptor for SPI transport bus interrupt.
CYGHWR_HAL_PLF_WWD_PIN_SPI_CS GPIO pin descriptor for SPI transport bus chip-select.
CYGHWR_HAL_PLF_WWD_PIN_SDIO_OOB_IRQ GPIO pin descriptor for SDIO transport bus interrupt.
CYGHWR_HAL_PLF_WWD_SDIO_ALIGN4 Manifest to control word-aligned transport bus transfers. This manifest may be needed for some platforms if the underlying platform transport bus implementation requires word-aligned memory buffers (e.g. due to DMA limitations).
CYGHWR_HAL_PLF_WWD_SDIO_SPEED Manifest defining the platform SDIO clock rate.

If the platform can support “out of application” storage of the WiFi firmware then the CDL option CYGFUN_NET_WIFI_BROADCOM_WWD_RESOURCES_INDIRECT will be configured, and the platform is then expected to provide manifests that map to the low-level firmware storage support. Normally such a large binary firmware image will be held in off-chip memory; but for certain architectures it may just be held in a specific region of some on-chip flash memory.

Table 199.3. Indirect firmware access

HAL_PLF_WIFI_BROADCOM_WWD_INDIRECT_FW_READ The platform specific function used to read an amount of raw firmware data from a logical byte offset.
HAL_PLF_WIFI_BROADCOM_WWD_LL_INIT If required the function to be called to perform low-level memory system initialisation prior to the WWD layer performing indirect firmware reads.