Part II. The eCos Hardware Abstraction Layer (HAL)
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Part II. The eCos Hardware Abstraction Layer (HAL)

Table of Contents

1. Introduction
2. Architecture, Variant and Platform
3. General principles
4. HAL Interfaces
4.1. Base Definitions
4.1.1. Byte order
4.1.2. Label Translation
4.1.3. Base types
4.1.4. Atomic types
4.2. Architecture Characterization
4.2.1. Register Save Format
4.2.2. Thread Context Initialization
4.2.3. Thread Context Switching
4.2.4. Bit indexing
4.2.5. Idle thread activity
4.2.6. Reorder barrier
4.2.7. Breakpoint support
4.2.8. GDB support
4.2.9. Setjmp and longjmp support
4.2.10. Stack Sizes
4.2.11. Address Translation
4.2.12. Global Pointer
4.3. Interrupt Handling
4.3.1. Vector numbers
4.3.2. Interrupt state control
4.3.3. ISR and VSR management
4.3.4. Interrupt controller management
4.4. Clocks and Timers
4.4.1. Clock Control
4.4.2. Microsecond Delay
4.4.3. Clock Frequency Definition
4.5. HAL I/O
4.5.1. Register address
4.5.2. Register read
4.5.3. Register write
4.6. HAL Unique-ID
4.6.1. HAL_UNIQUE_ID_LEN
4.6.2. HAL_UNIQUE_ID
4.7. Cache Control
4.7.1. Cache Dimensions
4.7.2. Global Cache Control
4.7.3. Cache Line Control
4.8. Linker Scripts
4.9. Diagnostic Support
4.10. SMP Support
4.10.1. Target Hardware Limitations
4.10.2. HAL Support
5. Exception Handling
5.1. HAL Startup
5.2. Vectors and VSRs
5.3. Default Synchronous Exception Handling
5.4. Default Interrupt Handling
6. HAL GDB File I/O Routines
HAL GDB File I/O Routines — access host file system
7. Porting Guide
7.1. Introduction
7.2. HAL Structure
7.2.1. HAL Classes
7.2.2. File Descriptions
7.3. Virtual Vectors (eCos/ROM Monitor Calling Interface)
7.3.1. Virtual Vectors
7.3.2. The COMMS channels
7.3.3. The calling Interface API
7.3.4. IO channels
7.4. HAL Coding Conventions
7.4.1. Implementation issues
7.4.2. Source code details
7.4.3. Nested Headers
7.5. Platform HAL Porting
7.5.1. HAL Platform Porting Process
7.5.2. HAL Platform CDL
7.5.3. Platform Memory Layout
7.5.4. Platform Serial Device Support
7.6. Variant HAL Porting
7.6.1. HAL Variant Porting Process
7.6.2. HAL Variant CDL
7.6.3. Cache Support
7.7. Architecture HAL Porting
7.7.1. HAL Architecture Porting Process
7.7.2. CDL Requirements
8. Future developments
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