| Chapter 2. Architecture, Variant and Platform | ||
|---|---|---|
 | Part II. The eCos Hardware Abstraction Layer (HAL) |  |
Chapter 2. Architecture, Variant and Platform
We have identified three levels at which the HAL must operate.
- The architecture HAL abstracts the basic CPU architecture and includes things like interrupt delivery, context switching, CPU startup etc.
- The variant HAL encapsulates features of the CPU variant such as caches, MMU and FPU features. It also deals with any on-chip peripherals such as memory and interrupt controllers. For architectural variations, the actual implementation of the variation is often in the architectural HAL, and the variant HAL simply provides the correct configuration definitions.
- The platform HAL abstracts the properties of the current platform and includes things like platform startup, timer devices, I/O register access and interrupt controllers.
The boundaries between these three HAL levels are necessarily blurred since functionality shifts between levels on a target-by-target basis. For example caches and MMU may be either an architecture feature or a variant feature. Similarly, memory and interrupt controllers may be on-chip and in the variant HAL, or off-chip and in the platform HAL.
Generally there is a separate package for each of the architecture, variant and package HALs for a target. For some of the older targets, or where it would be essentially empty, the variant HAL is omitted.
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| Chapter 1. Introduction |  | Chapter 3. General principles |
| 2024-12-10 | Open Publication License |