The HAL Port
Prev Chapter 360. STMicroelectronics ST40 Evaluation Board Support Next

Name

HAL Port — Implementation Details

Overview

This documentation explains how the eCos HAL specification has been mapped onto the ST40EB hardware, and should be read in conjunction with that specification. The ST40EB platform HAL package complements the SH architectural HAL and the SH4 variant HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM startup, the HAL will perform additional initialization, setting up the external SDRAM and programming the various internal registers including clocks, EMI and LMI. The values used for most of these registers are assigned fixed values from a table in the header cyg/hal/platform.inc.

Linker Scripts and Memory Maps

The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

off-chip Flash
This is located at address 0x00000000 of the physical memory space and is therefore accessible in the P1 region at location 0x80000000. An uncached shadow of this memory is available in the P2 region at 0xA0000000. The contents of the flash are organized as described earlier.
external SDRAM
This is located at address 0x08000000 of the physical memory space and is therefore accessable in the P1 region at location 0x88000000. An uncached shadow of this memory is available in the P2 region at 0xA8000000. The first 256 bytes are used for hardware exception vectors. The next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. For ROM startup, all remaining SDRAM is available. For RAM startup, available SDRAM starts at location 0x80020000, with the bottom 128Kbytes reserved for use by RedBoot.
on-chip peripherals
These are accessible via the P4 region at location 0xE0000000 onwards. The on-chip PCI controller is located at base address in the P2 region at 0xB0000000, and a memory-mapped view of the PCI space configuration registers at 0xB7000000. Other base addresses of on-chip peripherals can be found in the ST40RA datasheet (P/N: ADCS 7260755H).
off-chip peripherals
All off-chip peripherals used by eCos are accessed via on-chip bus controllers such as LMI, EMI or PCI. All others are left untouched.

Clock Support

The platform HAL provides configuration options for the eCos system clock. This always uses the hardware timer 0, which should not be used directly by application code. Timer 1 is used to implement a microsecond resolution busy delay service. Timer 2 is not used by eCos so application code is free to manipulate this as required. The actual HAL macros for managing the clock are provided by the SH architecture processor HAL.

There is a software model of the structure of the SH family clock supply subsystem which performs the correct calculations to yield not only the inputs for the CPU clock but also the peripheral clocks fed to the serial device, memory controllers and other devices. The values for the master crystal, the PLL multipliers and various dividers are supplied by the platform HAL. Some care must be taken in defining these since wrong values will cause the timers and the SCIF baud rate to be miscalculated (resulting visibly in garbage on the serial output).

The ST40 extends the SH family clock model by providing a CLOCKGEN subsystem allowing the hardware clock frequency to be controlled. The CLOCKGENA.PLL1CR register is the primary means to do this, and is initialised by switches 1, 2 and 3 on DIP switch block SW3. As the ST40EB is fitted with an ST40RA166 processor, it is assumed that a speed of 166MHz has been selected. This corresponds to SW3-1 set to OFF, SW3-2, set to OFF and SW3-3 set to ON.

If the DIP switches are changed from the default then the value of CYGHWR_HAL_SH_OOC_XTAL must be changed to match. Consult the ST40RA documentation on appropriate values for the clock and associated divider options for the subclocks if you wish these to be altered from the default.

Other Issues

The ST40EB platform HAL does not affect the implementation of other parts of the eCos HAL specification. The SH4 variant HAL, and the SH architectural HAL documentation should be consulted for further details.

It should be noted that the floating point support in the SH HAL has a caveat that, if the FPSCR register is changed, it may get reverted at a later stage by certain operations performed by the GCC compiler. This behaviour is intentional as the alternative would be to update the GCC compiler's internal state about the FPSCR at every context switch which would be expensive for a feature that is unlikely to be used frequently. If the FPSCR is to be changed by the application, the developer should call the function __set_fpscr(int), passing it the new FPSCR value.

Prev Up Next
Configuration Home Part LXXXVII. TILE-Gx Architecture