HAL Port — Implementation Details
This documentation explains how the eCos HAL specification has been mapped onto the STM3210E-EVAL board hardware, and should be read in conjunction with that specification. The STM3210E-EVAL platform HAL package complements the ARM architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.
Following a hard or soft reset the HAL will initialize or reinitialize many of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROM and JTAG startup, the HAL will perform additional
initialization, programming the various internal registers
including the PLL, peripheral clocks and GPIO pins. The details
of the early hardware startup may be found in the
src/stm3210e_eval_misc.c in both
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- External RAM
This is located at address 0x68000000 of the memory space, and
is 1MiB long. For ROM applications, all of RAM is available for
use. For RAM startup applications, RAM below 0x68008000 is
reserved for RedBoot and the top
CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZEbytes are reserved for the interrupt stack, the remainder is available for the application.
- External FLASH
- This is located at address 0x64000000 of the memory space and is 4MiB in size. Since RedBoot is normally programmed into the internal flash this memory is entirely available for application use and may be managed by the FIS flash file system.
- Internal RAM
This is located at address 0x20000000 of the memory space, and
is 64KiB in size. The eCos VSR table occupies the bottom 512
bytes. The virtual vector table starts at 0x00000100 and
extends to 0x00000200. For ROM and JTAG startups, the top
CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZEbytes are reserved for the interrupt stack. The remainder of internal RAM is available for use by applications.
- Internal FLASH
- This is located at address 0x08000000 of the memory space and will be mapped to 0x00000000 at reset. This region is 512KiB in size. ROM applications are by default configured to run from this memory. This memory is not managed by RedBoot's FIS system, but it can be written using the fis write command and erased using the fis erase command.
- On-Chip Peripherals
- These are accessible at locations 0x40000000 and 0xE0000000 upwards. Descriptions of the contents can be found in the STM32 User Manual.
The platform linker scripts define the following symbols:
- This defines the location of the VSR table. This is set to 0x20000000 for all startup types, and space for 128 entries is reserved.
- This defines the location of the virtual vector table used to communicate between an ROM monitor and an eCos application. This is allocated right after the VSR table, at 0x20000100. To permit expansion and possible addition of other tables, the linker scripts then allocate further sections from 0x20000400.
- This defines the location of the interrupt stack. For ROM and JTAG startups, this is allocated to the top of internal SRAM, 0x20010000. For RAM startups, it is allocated to the top of external SRAM, 0x68100000.
- This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.
|2023-08-15||eCosPro Non-Commercial Public License|