| The HAL Port | ||
|---|---|---|
 | Chapter 307. STM32H7 Nucleo-144 Platform HAL |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the STM32H7 Nucleo-144 board hardware, and should be read in conjunction with that specification. The NUCLEO-144 Board HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset the HAL will initialize or
reinitialize many of the on-chip peripherals.
For both ROM
and JTAG startup types the HAL will perform
all initialization, programming the various internal registers
including the PLLs, peripheral clocks and GPIO pins. The details of the
early hardware startup may be found in
the src/nucleo144_misc.c in
both hal_system_init
and hal_platform_init.
Memory Map
The platform HAL package provides the memory layout information needed
to generate the linker script. For all the STARTUP variations the
top CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes
of the on-chip SRAM are reserved for the interrupt stack. The
remainder of the internal SRAM is available for use by
applications. The key memory locations are as follows:
- Internal RAM
This is located at address
0x24000000of the memory space, and is 320KiB in size. The eCos VSR table occupies the bottom 716-bytes of memory, with the virtual vector table starting at0x240002CCand extending to0x240003CC.This memory region comprises two contiguous memory blocks, the 128kiB AXI-SRAM plus 192kiB of shared SRAM in the default configuration where it is assigned to the AXI-SRAM.
- SRAM1
-
This is located at address
0x30000000of the memory space, and is 16KiB in size. This is used to contain the Ethernet transmit and receive descriptor rings. It is mapped by an MPU region that disables caching for accesses. - Internal FLASH
-
This is located at address
0x08000000of the memory space and will be mapped to0x00000000at reset. This region is 1024KiB in size.ROMapplications are by default configured to run from this memory. The 256kiB from offset 0xC0000 is used for flash testing. The test space is defined in__NUCLEO144_FLASHTEST_ONCHIPinplf_io.h. - QSPI NOR Flash
-
The QSPI NOR flash is accessible through the flash
API. The 256kiB from offset 0x100000 is used for flash
testing. The test space is defined in
__NUCLEO144_FLASHTEST_OCTOSPIinplf_io.h. - On-Chip Peripherals
-
These are accessible at locations
0x40000000and0xE0000000upwards. Descriptions of the contents can be found in the STM32 User Manual.
Linker Scripts
The platform linker scripts define the following symbols:
- hal_vsr_table
-
This defines the location of the VSR table. This is set
to
0x20000000for all startup types, and space for 114 entries is reserved. - hal_virtual_vector_table
-
This defines the location of the virtual vector table used to
communicate between an ROM monitor and an eCos application. This is
allocated right after the VSR table, at
0x240002cc. - hal_interrupt_stack
-
This defines the location of the interrupt stack. This is allocated to
the top of internal SRAM,
0x24050000. - hal_startup_stack
- This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.
Flash wait states
The STM32H7 Nucleo-144 platform HAL provides a configuration option to
set the number of Flash read wait states to
use: CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It
is important to verify and if necessary update this value if changing
the CPU clock (HCLK) frequency or CPU voltage. Consult the relevant
STM32 datasheets and programming manuals for the STM32H723 parts for
appropriate values for different clock speeds or voltages. The default
of 5 reflects the default HCLK frequency.
Real-time characterization
The tm_basic kernel test gives statistics gathered
about the real-time characterization and performance of the
kernel. The sample output is shown here for information. The test was
built for ROM startup with optimization flag
-O2, since it provides the best performance as both code and data
could remain on-chip.
Example 307.1. nucleo144_stm32h723 Real-time characterization
Startup, main thrd : stack used 356 size 2048
Startup : Idlethread stack used 76 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 1.00 microseconds (1 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 15
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1088
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
INFO:<Ctrl-C disabled until test completion>
0.80 0.00 2.00 0.43 66% 26% Create thread
0.27 0.00 1.00 0.39 73% 73% Yield thread [all suspended]
0.27 0.00 1.00 0.39 73% 73% Suspend [suspended] thread
0.27 0.00 1.00 0.39 73% 73% Resume thread
0.27 0.00 1.00 0.39 73% 73% Set priority
0.07 0.00 1.00 0.12 93% 93% Get priority
0.53 0.00 1.00 0.50 53% 46% Kill [suspended] thread
0.27 0.00 1.00 0.39 73% 73% Yield [no other] thread
0.27 0.00 1.00 0.39 73% 73% Resume [suspended low prio] thread
0.27 0.00 1.00 0.39 73% 73% Resume [runnable low prio] thread
0.33 0.00 1.00 0.44 66% 66% Suspend [runnable] thread
0.20 0.00 1.00 0.32 80% 80% Yield [only low prio] thread
0.13 0.00 1.00 0.23 86% 86% Suspend [runnable->not runnable]
0.47 0.00 1.00 0.50 53% 53% Kill [runnable] thread
0.47 0.00 1.00 0.50 53% 53% Destroy [dead] thread
1.07 1.00 2.00 0.12 93% 93% Destroy [runnable] thread
1.20 1.00 2.00 0.32 80% 80% Resume [high priority] thread
0.40 0.00 1.00 0.48 60% 60% Thread switch
0.07 0.00 1.00 0.13 92% 92% Scheduler lock
0.20 0.00 1.00 0.31 80% 80% Scheduler unlock [0 threads]
0.19 0.00 1.00 0.30 81% 81% Scheduler unlock [1 suspended]
0.17 0.00 1.00 0.28 82% 82% Scheduler unlock [many suspended]
0.05 0.00 1.00 0.10 94% 94% Scheduler unlock [many low prio]
0.09 0.00 1.00 0.17 90% 90% Init mutex
0.25 0.00 1.00 0.38 75% 75% Lock [unlocked] mutex
0.25 0.00 1.00 0.38 75% 75% Unlock [locked] mutex
0.25 0.00 1.00 0.38 75% 75% Trylock [unlocked] mutex
0.22 0.00 1.00 0.34 78% 78% Trylock [locked] mutex
0.09 0.00 1.00 0.17 90% 90% Destroy mutex
2.00 2.00 2.00 0.00 100% 100% Unlock/Lock mutex
0.13 0.00 1.00 0.22 87% 87% Create mbox
0.09 0.00 1.00 0.17 90% 90% Peek [empty] mbox
0.25 0.00 1.00 0.38 75% 75% Put [first] mbox
0.09 0.00 1.00 0.17 90% 90% Peek [1 msg] mbox
0.25 0.00 1.00 0.38 75% 75% Put [second] mbox
0.06 0.00 1.00 0.12 93% 93% Peek [2 msgs] mbox
0.28 0.00 1.00 0.40 71% 71% Get [first] mbox
0.19 0.00 1.00 0.30 81% 81% Get [second] mbox
0.25 0.00 1.00 0.38 75% 75% Tryput [first] mbox
0.19 0.00 1.00 0.30 81% 81% Peek item [non-empty] mbox
0.22 0.00 1.00 0.34 78% 78% Tryget [non-empty] mbox
0.22 0.00 1.00 0.34 78% 78% Peek item [empty] mbox
0.22 0.00 1.00 0.34 78% 78% Tryget [empty] mbox
0.06 0.00 1.00 0.12 93% 93% Waiting to get mbox
0.06 0.00 1.00 0.12 93% 93% Waiting to put mbox
0.13 0.00 1.00 0.22 87% 87% Delete mbox
1.16 1.00 2.00 0.26 84% 84% Put/Get mbox
0.03 0.00 1.00 0.06 96% 96% Init semaphore
0.16 0.00 1.00 0.26 84% 84% Post [0] semaphore
0.25 0.00 1.00 0.38 75% 75% Wait [1] semaphore
0.19 0.00 1.00 0.30 81% 81% Trywait [0] semaphore
0.25 0.00 1.00 0.38 75% 75% Trywait [1] semaphore
0.03 0.00 1.00 0.06 96% 96% Peek semaphore
0.03 0.00 1.00 0.06 96% 96% Destroy semaphore
1.00 1.00 1.00 0.00 100% 100% Post/Wait semaphore
0.06 0.00 1.00 0.12 93% 93% Create counter
0.09 0.00 1.00 0.17 90% 90% Get counter value
0.09 0.00 1.00 0.17 90% 90% Set counter value
0.22 0.00 1.00 0.34 78% 78% Tick counter
0.06 0.00 1.00 0.12 93% 93% Delete counter
0.09 0.00 1.00 0.17 90% 90% Init flag
0.22 0.00 1.00 0.34 78% 78% Destroy flag
0.19 0.00 1.00 0.30 81% 81% Mask bits in flag
0.22 0.00 1.00 0.34 78% 78% Set bits in flag [no waiters]
0.25 0.00 1.00 0.38 75% 75% Wait for flag [AND]
0.22 0.00 1.00 0.34 78% 78% Wait for flag [OR]
0.31 0.00 1.00 0.43 68% 68% Wait for flag [AND/CLR]
0.28 0.00 1.00 0.40 71% 71% Wait for flag [OR/CLR]
0.06 0.00 1.00 0.12 93% 93% Peek on flag
0.13 0.00 1.00 0.22 87% 87% Create alarm
0.31 0.00 1.00 0.43 68% 68% Initialize alarm
0.16 0.00 1.00 0.26 84% 84% Disable alarm
0.34 0.00 1.00 0.45 65% 65% Enable alarm
0.13 0.00 1.00 0.22 87% 87% Delete alarm
0.28 0.00 1.00 0.40 71% 71% Tick counter [1 alarm]
0.91 0.00 1.00 0.17 90% 9% Tick counter [many alarms]
0.41 0.00 1.00 0.48 59% 59% Tick & fire counter [1 alarm]
5.81 5.00 6.00 0.31 81% 18% Tick & fire counters [>1 together]
1.06 1.00 2.00 0.12 93% 93% Tick & fire counters [>1 separately]
1.00 1.00 1.00 0.00 100% 100% Alarm latency [0 threads]
1.00 1.00 1.00 0.00 100% 100% Alarm latency [2 threads]
1.00 1.00 1.00 0.00 100% 100% Alarm latency [many threads]
2.00 2.00 2.00 0.00 100% 100% Alarm -> thread resume latency
0.00 0.00 0.00 0.00 Clock/interrupt latency
1.00 1.00 1.00 0.00 Clock DSR latency
204 180 220 Worker thread stack used (stack size 1088)
All done, main thrd : stack used 696 size 2048
All done : Idlethread stack used 172 size 1280
Timing complete - 29810 ms total
PASS:<Basic timing OK>
EXIT:<done>
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| Hardware debugging support |  | Test Programs |
| 2024-12-10 | eCosPro Non-Commercial Public License |