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Previous: typedef arelent, Up: Relocations [Contents][Index]
When an application wants to create a relocation, but doesn’t know what the target machine might call it, it can find out by using this bit of code.
bfd_reloc_code_type
Description
The insides of a reloc code. The idea is that, eventually, there
will be one enumerator for every type of relocation we ever do.
Pass one of these values to bfd_reloc_type_lookup, and it’ll
return a howto pointer.
This does mean that the application must determine the correct enumerator value; you can’t get a howto pointer from a random set of attributes.
Here are the possible values for enum bfd_reloc_code_real:
Basic absolute relocations of N bits.
PC-relative relocations. Sometimes these are relative to the address of the relocation itself; sometimes they are relative to the start of the section containing the relocation. It depends on the specific target.
The 24-bit relocation is used in some Intel 960 configurations.
For ELF.
Relocations used by 68K ELF.
Linkage-table relative.
These PC-relative relocations are stored as word displacements – i.e., byte displacements shifted right two bits. The 30-bit word displacement (<<32_PCREL_S2>> – 32 bits, shifted 2) is used on the SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The signed 16-bit displacement is used on the MIPS, and the 23-bit displacement is used on the Alpha.
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of the target word. These are used on the SPARC.
For systems that allocate a Global Pointer register, these are displacements off that register. These relocation types are handled specially, because the value the register will have is decided relatively late.
SPARC ELF relocations. There is probably some overlap with other relocation types already defined.
I think these are specific to SPARC a.out (e.g., Sun 4).
SPARC64 relocations
SPARC TLS relocations
SPU Relocations.
Alpha ECOFF and ELF relocations. Some of these treat the symbol or "addend" in some special way. For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when writing; when reading, it will be the absolute section symbol. The addend is the displacement in bytes of the "lda" instruction from the "ldah" instruction (which is at the address of this reloc).
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as with GPDISP_HI16 relocs. The addend is ignored when writing the relocations out, and is filled in with the file’s GP value on reading, for convenience.
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 relocation except that there is no accompanying GPDISP_LO16 relocation.
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; the assembler turns it into a LDQ instruction to load the address of the symbol, and then fills in a register in the real instruction.
The LITERAL reloc, at the LDQ instruction, refers to the .lita section symbol. The addend is ignored when writing, but is filled in with the file’s GP value on reading, for convenience, as with the GPDISP_LO16 reloc.
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. It should refer to the symbol to be referenced, as with 16_GOTOFF, but it generates output not based on the position within the .got section, but relative to the GP value chosen for the file during the final link stage.
The LITUSE reloc, on the instruction using the loaded address, gives information to the linker that it might be able to use to optimize away some literal section references. The symbol is ignored (read as the absolute section symbol), and the "addend" indicates the type of instruction using the register: 1 - "memory" fmt insn 2 - byte-manipulation (byte offset reg) 3 - jsr (target of branch)
The HINT relocation indicates a value that should be filled into the "hint" field of a jmp/jsr/ret instruction, for possible branch- prediction logic which may be provided on some processors.
The LINKAGE relocation outputs a linkage pair in the object file, which is filled by the linker.
The CODEADDR relocation outputs a STO_CA in the object file, which is filled by the linker.
The GPREL_HI/LO relocations together form a 32-bit offset from the GP register.
Like BFD_RELOC_23_PCREL_S2, except that the source and target must share a common GP, and the target address is adjusted for STO_ALPHA_STD_GPLOAD.
The NOP relocation outputs a NOP if the longword displacement between two procedure entry points is < 2^21.
The BSR relocation outputs a BSR if the longword displacement between two procedure entry points is < 2^21.
The LDA relocation outputs a LDA if the longword displacement between two procedure entry points is < 2^16.
The BOH relocation outputs a BSR if the longword displacement between two procedure entry points is < 2^21, or else a hint.
Alpha thread-local storage relocations.
High 16 bits of 32-bit value but the low 16 bits will be sign extended and added to form the final result. If the low 16 bits form a negative number, we need to add one to the high value to compensate for the borrow when the low bits are added.
Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 16-bit immediate fields
MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign extended and added to form the final result. If the low 16 bits form a negative number, we need to add one to the high value to compensate for the borrow when the low bits are added.
MIPS16 TLS relocations
microMIPS PC-relative relocations.
MIPS PC-relative relocations.
microMIPS versions of generic BFD relocs.
MIPS ELF relocations.
FT32 ELF relocations.
Fujitsu Frv Relocations.
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes in the instruction.
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes in the instruction.
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes in the instruction.
Together with another reloc targeted at the same location, allows for a value that is the difference of two symbols in the same section.
The addend of this reloc is an alignment power that must be honoured at the offset’s location, regardless of linker relaxation.
Various TLS-related relocations.
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the instruction.
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the instruction.
i386/elf relocations
x86-64/elf relocations
ns32k relocations
Picojava relocs. Not all of these appear in object files.
Power(rs6000) and PowerPC relocations.
PowerPC and PowerPC64 thread-local storage relocations.
The type of reloc used to build a constructor table - at the moment probably a 32 bit wide absolute relocation, but the target can choose. It generally does map to one of the other relocation types.
ARM 26 bit pc-relative branch. The lowest two bits must be zero and are not stored in the instruction.
ARM 26 bit pc-relative branch. The lowest bit must be zero and is not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction.
Thumb 22 bit pc-relative branch. The lowest bit must be zero and is not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction.
ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. The lowest bit must be zero and is not stored in the instruction. Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an "nn" one smaller in all cases. Note further that BRANCH23 corresponds to R_ARM_THM_CALL.
Pc-relative or absolute relocation depending on target. Used for entries in .init_array sections.
This reloc is used for references to RTTI data from exception handling tables. The actual definition depends on the target. It may be a pc-relative or some form of GOT-indirect relocation.
Low and High halfword relocations for MOVW and MOVT instructions.
Relocations for setting up GOTs and PLTs for shared libraries.
ARM thread-local storage relocations.
ARM group relocations.
Thumb1 relocations to support execute-only code.
These relocs are only used within the ARM assembler. They are not (at present) written to any object files.
Renesas / SuperH SH relocs. Not all of these appear in object files.
ARC relocs.
ADI Blackfin FD-PIC relocations.
Mitsubishi D10V relocs. This is a 10-bit reloc with the right 2 bits assumed to be 0.
Mitsubishi D10V relocs. This is a 10-bit reloc with the right 2 bits assumed to be 0. This is the same as the previous reloc except it is in the left container, i.e., shifted left 15 bits.
This is a 6-bit pc-relative reloc with the right 3 bits assumed to be 0. Same as the previous reloc but on the right side of the container.
This is a 12-bit pc-relative reloc with the right 3 bits assumed to be 0. Same as the previous reloc but on the right side of the container.
This is an 18-bit pc-relative reloc with the right 3 bits assumed to be 0.
This is an 18-bit pc-relative reloc with the right 3 bits assumed to be 0. Same as the previous reloc but on the right side of the container.
Renesas M16C/M32C Relocations.
Renesas M32R (formerly Mitsubishi M32R) relocs. This is a 24 bit absolute address.
This is a 16-bit reloc containing the high 16 bits of an address used when the lower 16 bits are treated as unsigned.
This is a 16-bit reloc containing the high 16 bits of an address used when the lower 16 bits are treated as signed.
This is a 16-bit reloc containing the small data area offset for use in add3, load, and store instructions.
For PIC.
This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
This is a 20-bit reloc containing the high 20 bits of an address used with the lower 12 bits
This is a 12-bit reloc containing the lower 12 bits of an address then shift right by 3. This is used with ldi,sdi...
This is a 12-bit reloc containing the lower 12 bits of an address then shift left by 2. This is used with lwi,swi...
This is a 12-bit reloc containing the lower 12 bits of an address then shift left by 1. This is used with lhi,shi...
This is a 12-bit reloc containing the lower 12 bits of an address then shift left by 0. This is used with lbisbi...
This is a 12-bit reloc containing the lower 12 bits of an address then shift left by 0. This is only used with branch relaxations
This is a 15-bit reloc containing the small data area 18-bit signed offset and shift left by 3 for use in ldi, sdi...
This is a 15-bit reloc containing the small data area 17-bit signed offset and shift left by 2 for use in lwi, swi...
This is a 15-bit reloc containing the small data area 16-bit signed offset and shift left by 1 for use in lhi, shi...
This is a 15-bit reloc containing the small data area 15-bit signed offset and shift left by 0 for use in lbi, sbi...
This is a 16-bit reloc containing the small data area 16-bit signed offset and shift left by 3
This is a 17-bit reloc containing the small data area 17-bit signed offset and shift left by 2 for use in lwi.gp, swi.gp...
This is a 18-bit reloc containing the small data area 18-bit signed offset and shift left by 1 for use in lhi.gp, shi.gp...
This is a 19-bit reloc containing the small data area 19-bit signed offset and shift left by 0 for use in lbi.gp, sbi.gp...
for PIC
for relax
for PIC
for floating point
for dwarf2 debug_line.
for PIC object relaxation
This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
relaxation relative relocation types
For ex9 and ifc using.
For TLS.
This is a 16 bit offset (of which only 15 bits are used) from the short data area pointer.
This is a 16 bit offset (of which only 15 bits are used) from the zero data area pointer.
This is an 8 bit offset (of which only 6 bits are used) from the tiny data area pointer.
This is an 8bit offset (of which only 7 bits are used) from the tiny data area pointer.
This is a 5 bit offset (of which only 4 bits are used) from the tiny data area pointer.
This is a 16 bit offset from the short data area pointer, with the bits placed non-contiguously in the instruction.
This is a 16 bit offset from the zero data area pointer, with the bits placed non-contiguously in the instruction.
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu instructions.
This is a 8bit DP reloc for the tms320c30, where the most significant 8 bits of a 24 bit word are placed into the least significant 8 bits of the opcode.
This is a 7bit reloc for the tms320c54x, where the least significant 7 bits of a 16 bit word are placed into the least significant 7 bits of the opcode.
This is a 9bit DP reloc for the tms320c54x, where the most significant 9 bits of a 16 bit word are placed into the least significant 9 bits of the opcode.
This is a 16-bit reloc for the tms320c54x, where the least significant 16 bits of a 23-bit extended address are placed into the opcode.
This is a reloc for the tms320c54x, where the most significant 7 bits of a 23-bit extended address are placed into the opcode.
TMS320C6000 relocations.
This is a 32 bit reloc for the FR30 that stores 20 bits split up into two sections.
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 4 bits.
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset into 8 bits.
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset into 8 bits.
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset into 8 bits.
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative short offset into 8 bits.
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative short offset into 11 bits.
Motorola Mcore relocations.
Toshiba Media Processor Relocations.
Imagination Technologies Meta relocations.
These are relocations for the GETA instruction.
These are relocations for a conditional branch instruction.
These are relocations for the PUSHJ instruction.
These are relocations for the JMP instruction.
This is a relocation for a relative address as in a GETA instruction or a branch.
This is a relocation for an instruction field that may be a general register or a value 0..255.
This is a relocation for two instruction fields holding a register and an offset, the equivalent of the relocation.
This relocation is an assertion that the expression is not allocated as a global register. It does not modify contents.
This is a 16 bit reloc for the AVR that stores 8 bit pc relative short offset into 7 bits.
This is a 16 bit reloc for the AVR that stores 13 bit pc relative short offset into 12 bits.
This is a 16 bit reloc for the AVR that stores 17 bit value (usually program memory address) into 16 bits.
This is a 16 bit reloc for the AVR that stores 8 bit value (usually data memory address) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit of data memory address) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit of program memory address) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit of 32 bit value) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (usually data memory address) into 8 bit immediate value of SUBI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (high 8 bit of data memory address) into 8 bit immediate value of SUBI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (most high 8 bit of program memory address) into 8 bit immediate value of LDI or SUBI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb of 32 bit value) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores 8 bit value (usually command address) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores 8 bit value (command address) into 8 bit immediate value of LDI insn. If the address is beyond the 128k boundary, the linker inserts a jump stub for this reloc in the lower 128k.
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit of command address) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit of command address) into 8 bit immediate value of LDI insn. If the address is beyond the 128k boundary, the linker inserts a jump stub for this reloc below 128k.
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit of command address) into 8 bit immediate value of LDI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (usually command address) into 8 bit immediate value of SUBI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (high 8 bit of 16 bit command address) into 8 bit immediate value of SUBI insn.
This is a 16 bit reloc for the AVR that stores negated 8 bit value (high 6 bit of 22 bit command address) into 8 bit immediate value of SUBI insn.
This is a 16 bit reloc for the AVR that stores all needed bits for absolute addressing with ldi with overflow check to linktime
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw instructions
This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol in .byte lo8(symbol)
This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol in .byte hi8(symbol)
This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol in .byte hlo8(symbol)
AVR relocations to mark the difference of two local symbols. These are only needed to support linker relaxation and can be ignored when not relaxing. The field is set to the value of the difference assuming no relaxation. The relocation encodes the position of the second symbol so the linker can determine whether to adjust the field value.
This is a 7 bit reloc for the AVR that stores SRAM address for 16bit lds and sts instructions supported only tiny core.
This is a 6 bit reloc for the AVR that stores an I/O register number for the IN and OUT instructions
This is a 5 bit reloc for the AVR that stores an I/O register number for the SBIC, SBIS, SBI and CBI instructions
RISC-V relocations.
Renesas RL78 Relocations.
Renesas RX Relocations.
s390 tls relocations.
Long displacement extension.
This is a 24-bit reloc with the right 1 bit assumed to be 0
Undocumented Score relocs
Scenix IP2K - ext/low/high 8 bits of data address
Scenix IP2K - low/high 8 bits of instruction word address
Scenix VPE4K coprocessor - data/insn-space addressing
These two relocations are used by the linker to determine which of the entries in a C++ virtual function table are actually used. When the –gc-sections option is given, the linker will zero out the entries that are not used, so that the code for those functions need not be included in the output.
VTABLE_INHERIT is a zero-space relocation used to describe to the linker the inheritance tree of a C++ virtual function table. The relocation’s symbol should be the parent class’ vtable, and the relocation should be located at the child vtable.
VTABLE_ENTRY is a zero-space relocation that describes the use of a virtual function table entry. The reloc’s symbol should refer to the table of the class mentioned in the code. Off of that base, an offset describes the entry that is being used. For Rela hosts, this offset is stored in the reloc’s addend. For Rel hosts, we are forced to put this offset in the reloc’s section offset.
Intel IA64 Relocations.
Motorola 68HC11 reloc. This reloc marks the beginning of a jump/call instruction. It is used for linker relaxation to correctly identify beginning of instruction and change some branches to use PC-relative addressing mode.
Motorola 68HC11 reloc. This reloc marks a group of several instructions that gcc generates and for which the linker relaxation pass can modify and/or remove some of them.
Motorola 68HC11 reloc. This is the 16-bit lower part of an address. It is used for ’call’ instruction to specify the symbol address without any special transformation (due to memory bank window).
Motorola 68HC11 reloc. This is a 8-bit reloc that specifies the page number of an address. It is used by ’call’ instruction to specify the page number of the symbol.
Motorola 68HC11 reloc. This is a 24-bit reloc that represents the address with a 16-bit value and a 8-bit page number. The symbol address is transformed to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
Freescale XGATE reloc. This reloc marks the beginning of a bra/jal instruction.
Freescale XGATE reloc. This reloc marks a group of several instructions that gcc generates and for which the linker relaxation pass can modify and/or remove some of them.
Freescale XGATE reloc. This is the 16-bit lower part of an address. It is used for the ’16-bit’ instructions.
Freescale XGATE reloc. This is the 16-bit lower part of an address. It is used for the ’16-bit’ instructions.
Freescale XGATE reloc. This is the 16-bit higher part of an address. It is used for the ’16-bit’ instructions.
Motorola 68HC12/XGATE reloc. This is the 8 bit low part of an absolute address and immediately precedes a matching HI8XG part.
Motorola 68HC12/XGATE reloc. This is the 8 bit high part of an absolute address and immediately follows a matching LO8XG part.
NS CR16C Relocations.
NS CR16 Relocations.
NS CRX Relocations.
These relocs are only used within the CRIS assembler. They are not (at present) written to any object files.
Relocs used in ELF shared libraries for CRIS.
Relocs used in TLS code for CRIS.
Intel i860 Relocations.
OpenRISC 1000 Relocations.
H8 elf Relocations.
Sony Xstormy16 Relocations.
Infineon Relocations.
Relocations used by VAX ELF.
msp430 specific relocation codes
Relocations used by the Altera Nios II core.
PRU relocation for two consecutive LDI load instructions that load a 32 bit value into a register. If the higher bits are all zero, then the second instruction may be relaxed.
PRU Program Memory relocations. Used to convert from byte addressing to 32-bit word addressing.
PRU relocations to mark the difference of two local symbols. These are only needed to support linker relaxation and can be ignored when not relaxing. The field is set to the value of the difference assuming no relaxation. The relocation encodes the position of the second symbol so the linker can determine whether to adjust the field value. The PMEM variants encode the word difference, instead of byte difference between symbols.
IQ2000 Relocations.
Special Xtensa relocation used only by PLT entries in ELF shared objects to indicate that the runtime linker should set the value to one of its own internal functions or data structures.
Xtensa relocations for ELF shared objects.
Xtensa relocation used in ELF object files for symbols that may require PLT entries. Otherwise, this is just a generic 32-bit relocation.
Xtensa relocations to mark the difference of two local symbols. These are only needed to support linker relaxation and can be ignored when not relaxing. The field is set to the value of the difference assuming no relaxation. The relocation encodes the position of the first symbol so the linker can determine whether to adjust the field value.
Generic Xtensa relocations for instruction operands. Only the slot number is encoded in the relocation. The relocation applies to the last PC-relative immediate operand, or if there are no PC-relative immediates, to the last immediate operand.
Alternate Xtensa relocations. Only the slot is encoded in the relocation. The meaning of these relocations is opcode-specific.
Xtensa relocations for backward compatibility. These have all been replaced by BFD_RELOC_XTENSA_SLOT0_OP.
Xtensa relocation to mark that the assembler expanded the instructions from an original target. The expansion size is encoded in the reloc size.
Xtensa relocation to mark that the linker should simplify assembler-expanded instructions. This is commonly used internally by the linker after analysis of a BFD_RELOC_XTENSA_ASM_EXPAND.
Xtensa TLS relocations.
Lattice Mico32 relocations.
Difference between two section addreses. Must be followed by a BFD_RELOC_MACH_O_PAIR.
PCREL relocations. They are marked as branch to create PLT entry if required.
Used when loading a GOT entry with movq. It is specially marked so that the linker could optimize the movq to a leaq if possible.
This is a 32 bit reloc for the microblaze that stores the low 16 bits of a value
This is a 32 bit pc-relative reloc for the microblaze that stores the low 16 bits of a value
This is a 32 bit reloc for the microblaze that stores a value relative to the read-only small data area anchor
This is a 32 bit reloc for the microblaze that stores a value relative to the read-write small data area anchor
This is a 32 bit reloc for the microblaze to handle expressions of the form "Symbol Op Symbol"
This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). No relocation is done here - only used for relaxing
This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is PC-relative GOT offset
This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is GOT offset
This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is PC-relative offset into PLT
This is a 64 bit reloc that stores the 32 bit GOT relative value in two words (with an imm instruction). The relocation is relative offset from _GLOBAL_OFFSET_TABLE_
This is a 32 bit reloc that stores the 32 bit GOT relative value in a word. The relocation is relative offset from
This is used to tell the dynamic linker to copy the value out of the dynamic object into the runtime process image.
This is a 64 bit reloc that stores the 32 bit GOT relative value of the GOT TLS GD info entry in two words (with an imm instruction). The relocation is GOT offset.
This is a 64 bit reloc that stores the 32 bit GOT relative value of the GOT TLS LD info entry in two words (with an imm instruction). The relocation is GOT offset.
This is a 32 bit reloc for storing TLS offset to two words (uses imm instruction)
This is a 64 bit reloc that stores 32-bit thread pointer relative offset to two words (uses imm instruction).
This is a 64 bit reloc that stores 32-bit thread pointer relative offset to two words (uses imm instruction).
AArch64 pseudo relocation code to mark the start of the AArch64 relocation enumerators. N.B. the order of the enumerators is important as several tables in the AArch64 bfd backend are indexed by these enumerators; make sure they are all synced.
Basic absolute relocations of N bits. These are equivalent to BFD_RELOC_N and they were added to assist the indexing of the howto table.
PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL and they were added to assist the indexing of the howto table.
AArch64 MOV[NZK] instruction with most significant bits 0 to 15 of an unsigned address/value.
AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of an address/value. No overflow checking.
AArch64 MOV[NZK] instruction with most significant bits 16 to 31 of an unsigned address/value.
AArch64 MOV[NZK] instruction with less significant bits 16 to 31 of an address/value. No overflow checking.
AArch64 MOV[NZK] instruction with most significant bits 32 to 47 of an unsigned address/value.
AArch64 MOV[NZK] instruction with less significant bits 32 to 47 of an address/value. No overflow checking.
AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 of a signed or unsigned address/value.
AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a signed value. Changes instruction to MOVZ or MOVN depending on the value’s sign.
AArch64 MOV[NZ] instruction with most significant bits 16 to 31 of a signed value. Changes instruction to MOVZ or MOVN depending on the value’s sign.
AArch64 MOV[NZ] instruction with most significant bits 32 to 47 of a signed value. Changes instruction to MOVZ or MOVN depending on the value’s sign.
AArch64 Load Literal instruction, holding a 19 bit pc-relative word offset. The lowest two bits must be zero and are not stored in the instruction, giving a 21 bit signed byte offset.
AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page offset, giving a 4KB aligned page base address.
AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page offset, giving a 4KB aligned page base address, but with no overflow checking.
AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 8-bit load/store instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 14 bit pc-relative test bit and branch. The lowest two bits must be zero and are not stored in the instruction, giving a 16 bit signed byte offset.
AArch64 19 bit pc-relative conditional branch and compare & branch. The lowest two bits must be zero and are not stored in the instruction, giving a 21 bit signed byte offset.
AArch64 26 bit pc-relative unconditional branch. The lowest two bits must be zero and are not stored in the instruction, giving a 28 bit signed byte offset.
AArch64 26 bit pc-relative unconditional branch and link. The lowest two bits must be zero and are not stored in the instruction, giving a 28 bit signed byte offset.
AArch64 16-bit load/store instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 32-bit load/store instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 64-bit load/store instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 128-bit load/store instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 Load Literal instruction, holding a 19 bit PC relative word offset of the global offset table entry for a symbol. The lowest two bits must be zero and are not stored in the instruction, giving a 21 bit signed byte offset. This relocation type requires signed overflow checking.
Get to the page base of the global offset table entry for a symbol as part of an ADRP instruction using a 21 bit PC relative value.Used in conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
Unsigned 12 bit byte offset for 64 bit load/store from the page of the GOT entry for this symbol. Used in conjunction with BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
Unsigned 12 bit byte offset for 32 bit load/store from the page of the GOT entry for this symbol. Used in conjunction with BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry for this symbol. Valid in LP64 ABI only.
Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry for this symbol. Valid in LP64 ABI only.
Unsigned 15 bit byte offset for 64 bit load/store from the page of the GOT entry for this symbol. Valid in LP64 ABI only.
Scaled 14 bit byte offset to the page base of the global offset table.
Scaled 15 bit byte offset to the page base of the global offset table.
Get to the page base of the global offset table entry for a symbols tls_index structure as part of an adrp instruction using a 21 bit PC relative value. Used in conjunction with BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
Unsigned 12 bit byte offset to global offset table entry for a symbols tls_index structure. Used in conjunction with BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
Unsigned 12 bit byte offset to global offset table entry for a symbols tls_index structure. Used in conjunction with BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP instruction.
GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
bit[11:1] of byte offset to module TLS base address, encoded in ldst instructions.
Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
bit[11:2] of byte offset to module TLS base address, encoded in ldst instructions.
Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
bit[11:3] of byte offset to module TLS base address, encoded in ldst instructions.
Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
bit[11:0] of byte offset to module TLS base address, encoded in ldst instructions.
Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
AArch64 pseudo relocation code to mark the end of the AArch64 relocation enumerators that have direct mapping to ELF reloc codes. There are a few more enumerators after this one; those are mainly used by the AArch64 assembler for the internal fixup or to select one of the above enumerators.
AArch64 pseudo relocation code to be used internally by the AArch64 assembler and not (currently) written to any object files.
AArch64 unspecified load/store instruction, holding bits 0 to 11 of the address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
AArch64 pseudo relocation code for TLS local dynamic mode. It’s to be used internally by the AArch64 assembler and not (currently) written to any object files.
Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
AArch64 pseudo relocation code to be used internally by the AArch64 assembler and not (currently) written to any object files.
AArch64 pseudo relocation code to be used internally by the AArch64 assembler and not (currently) written to any object files.
AArch64 pseudo relocation code to be used internally by the AArch64 assembler and not (currently) written to any object files.
Tilera TILEPro Relocations.
Tilera TILE-Gx Relocations.
Visium Relocations.
WebAssembly relocations.
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
bfd_reloc_type_lookup
Synopsis
reloc_howto_type *bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); reloc_howto_type *bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name);
Description
Return a pointer to a howto structure which, when
invoked, will perform the relocation code on data from the
architecture noted.
bfd_default_reloc_type_lookup
Synopsis
reloc_howto_type *bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code);
Description
Provides a default relocation lookup routine for any architecture.
bfd_get_reloc_code_name
Synopsis
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
Description
Provides a printable name for the supplied relocation code.
Useful mainly for printing error messages.
bfd_generic_relax_section
Synopsis
bfd_boolean bfd_generic_relax_section
(bfd *abfd,
asection *section,
struct bfd_link_info *,
bfd_boolean *);
Description
Provides default handling for relaxing for back ends which
don’t do relaxing.
bfd_generic_gc_sections
Synopsis
bfd_boolean bfd_generic_gc_sections (bfd *, struct bfd_link_info *);
Description
Provides default handling for relaxing for back ends which
don’t do section gc – i.e., does nothing.
bfd_generic_lookup_section_flags
Synopsis
bfd_boolean bfd_generic_lookup_section_flags (struct bfd_link_info *, struct flag_info *, asection *);
Description
Provides default handling for section flags lookup
– i.e., does nothing.
Returns FALSE if the section should be omitted, otherwise TRUE.
bfd_generic_merge_sections
Synopsis
bfd_boolean bfd_generic_merge_sections (bfd *, struct bfd_link_info *);
Description
Provides default handling for SEC_MERGE section merging for back ends
which don’t have SEC_MERGE support – i.e., does nothing.
bfd_generic_get_relocated_section_contents
Synopsis
bfd_byte *bfd_generic_get_relocated_section_contents
(bfd *abfd,
struct bfd_link_info *link_info,
struct bfd_link_order *link_order,
bfd_byte *data,
bfd_boolean relocatable,
asymbol **symbols);
Description
Provides default handling of relocation effort for back ends
which can’t be bothered to do it efficiently.
_bfd_generic_set_reloc
Synopsis
void _bfd_generic_set_reloc
(bfd *abfd,
sec_ptr section,
arelent **relptr,
unsigned int count);
Description
Installs a new set of internal relocations in SECTION.
_bfd_unrecognized_reloc
Synopsis
bfd_boolean _bfd_unrecognized_reloc
(bfd * abfd,
sec_ptr section,
unsigned int r_type);
Description
Reports an unrecognized reloc.
Written as a function in order to reduce code duplication.
Returns FALSE so that it can be called from a return statement.
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