HAL Port — Implementation Details
This documentation explains how the eCos HAL specification has been mapped onto the SDK7780 hardware, and should be read in conjunction with that specification. The SDK7780 platform HAL package complements the SH architectural HAL and the SH4 variant HAL. It provides functionality which is specific to the target board.
Following a hard or soft reset the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROM startup, the HAL will perform additional initialization,
setting up the external SDRAM and programming the various internal
registers including clocks, EMI and LMI. The values used for most
of these registers are assigned fixed values from a table in the
The platform HAL provides configuration options for the eCos system clock. This always uses the hardware timer 0, which should not be used directly by application code. Timer 1 is used to implement a microsecond resolution busy delay service. Timers 2 to 5 are not used by eCos so application code is free to manipulate these as required. The actual HAL macros for managing the clock are provided by the SH architecture processor HAL.
There is a software model of the structure of the SH family clock supply subsystem which performs the correct calculations to yield not only the inputs for the CPU clock but also the peripheral clocks fed to the serial device, memory controllers and other devices. The values for the master crystal, the PLL multipliers and various dividers are supplied by the platform HAL. Some care must be taken in defining these since wrong values will cause the timers and the SCIF baud rate to be miscalculated (resulting visibly in garbage on the serial output).
The SH7780 extends the SH family clock model by providing a CLOCKGEN subsystem allowing the hardware clock frequency to be controlled. The CLOCKGENA.PLL1CR register is the primary means to do this, and is initialised by switches 1, 2, 3 and 7 on DIP switch block MD_SW. The delivery default settings for these switches is to select clock mode 0 giving a 400MHz CPU clock, 100MHz local bus and 50MHz peripheral clock.
If the DIP switches are changed from the default then the values of
CYGHWR_HAL_SH_OOC_DIVIDER_PFC must be changed to
The SDK7780 platform HAL does not affect the implementation of other parts of the eCos HAL specification. The SH4 variant HAL, and the SH architectural HAL documentation should be consulted for further details.
It should be noted that the floating point support in the SH HAL has a
caveat that, if the FPSCR register is changed, it may get reverted at a
later stage by certain operations performed by the GCC compiler. This
behaviour is intentional as the alternative would be to update the GCC
compiler's internal state about the FPSCR at every context switch which
would be expensive for a feature that is unlikely to be used frequently.
If the FPSCR is to be changed by the application, the developer
should call the function
__set_fpscr(int), passing it
the new FPSCR value.
|2022-03-29||eCosPro Non-Commercial Public License|