HAL Port — Implementation Details


This documentation explains how the eCos HAL specification has been mapped onto the Adder hardware, and should be read in conjunction with that specification. The Adder platform HAL package complements the PowerPC architectural HAL and the MPC8XX variant HAL. It provides functionality which is specific to the target board.


Following a hard or soft reset the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM or ROMRAM startup, the HAL will perform additional initialization, setting up the external RAM and programming the various internal registers. This is all done in the hal_hardware_init function in the assembler source file adder.S.

Linker Scripts and Memory Maps

The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

This is located at address 0xFE000000 of the physical memory space.
This is located at address 0x00000000 of the physical memory space. The first 12k bytes are used for hardware exception vectors. The next 512 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. For ROM/ROMRAM startup, all remaining SDRAM is available. For RAM startup, available RAM starts at location 0x00060000, with the bottom 384kB reserved for use by RedBoot.
on-chip peripherals
These are accessible via the CPU IMMR register, which is normally set to 0xFA200000. However, applications should not rely on this. See the documentation for the MPC850 or MPC852T for information on the on-chip peripherals.
off-chip peripherals
The Adder II has an MPC180 Encryption Processor on-board. However, this is not used by eCos.

Other Issues

The Adder platform HAL does not affect the implementation of other parts of the eCos HAL specification. The MPC8XX variant HAL, and the PowerPC architectural HAL documentation should be consulted for further details.