CYGPKG_HAL_MIPS_PNX8330 — eCos Support for the NXP PNX8330 Processor


The NXP PNX8330 processor is based around a 4KEc MIPS32 core, complemented by a range of on-chip peripherals. The HAL package CYGPKG_HAL_MIPS_PNX8330 provides the processor-specific support. It complements the MIPS architectural HAL package CYGPKG_HAL_MIPS, the MIPS32 variant package CYGPKG_HAL_MIPS_MIPS32 and the PNX83xx support package CYGPKG_HAL_MIPS_PNX83xx which contains support for features common to several members of the PNX83xx family. An eCos configuration should also include a platform HAL package to support board-level details like the memory chips and off-chip peripherals.


The PNX8330 HAL package should be loaded automatically when eCos is configured for appropriate target hardware. It should never be necessary to load this package explicitly. Unloading the package should only happen as a side effect of switching target hardware. The package does not contain any user-settable options.

The HAL Port

This section describes how the PNX8330 HAL package implements parts of the eCos HAL specification. It should be read in conjunction with similar sections from the architectural and variant HAL documentation.


The header file cyg/hal/pnx8330_io.h provides definitions of the on-chip peripherals used by eCos, except for some UART definitions which are provided by the PNX83xx support HAL instead. This header file is automatically included by the architectural header cyg/hal/hal_io.h, so typically application code and other packages will just include the latter. The register addresses are all in kseg1 so will be accessed uncached.

Interrupt Handling

The header file cyg/hal/pnx8330_intr.h provides ISR vector numbers for all interrupt sources, for example CYGNUM_HAL_ISR_I2C0 and CYGNUM_HAL_ISR_PIO_1. These vector numbers should be used for calls like cyg_interrupt_create. The header file is automatically included by the architectural header cyg/hal/hal_intr.h, and other packages and application code will normally just include the latter.

The interrupt vectors come in four groups. There are six vectors corresponding to the external interrupts available in the CPU SR and CAUSE registers. Of these, interrupt number 2 is attached to the on-chip interrupt controller, and interrupt number 5 is attached to the internal COMPARE register, which is used to supply system time interrupts. There are 37 vectors for the on-chip peripherals, managed by the priority interrupt controller. One of these, CYGNUM_HAL_ISR_PIO is reserved for use by the HAL's interrupt decoding code to detect PIO interrupts and decode them into the next 16 vectors. Another peripheral interrupt, CYGNUM_HAL_ISR_CONFIG is decoded into the final seven interrupt vectors, which correspond to the interrupt sources available from the CONFIG unit.

The eCos HAL macros HAL_INTERRUPT_MASK, HAL_INTERRUPT_UNMASK, HAL_INTERRUPT_ACKNOWLEDGE, HAL_INTERRUPT_CONFIGURE and HAL_INTERRUPT_SET_LEVEL are implemented by the processor HAL. The implementations depend on the interrupt vector. HAL_INTERRUPT_ACKNOWLEDGE is only needed for PIO and CONFIG interrupts, otherwise it is a no-op. HAL_INTERRUPT_CONFIGURE is only relevant for PIO interrupts.

Interrupt priorities should be in the range 1 to 14, and correspond to the int_priority fields in the pic_int_reg registers. 1 is the lowest priority and 14 the highest. Interrupt priorities are ignored for the COMPARE interrupt. All PIO and CONFIG interrupt sources operate at the same priority, which is the highest priority assigned to any of the PIO or CONFIG vectors.

Interrupt chaining via the common HAL's configuration option CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN is supported for PIO interrupts only. This makes it possible to connect several external peripherals' interrupt lines to a single PIO pin if desired.

Clock Support

The 4kEc core provides standard COUNTER and COMPARE registers which are used for the eCos system clock. The CONFIG unit timer 0 is used for gprof-based profiling if enabled, otherwise it can be used by the application. The CONFIG unit watchdog timer is supported by a watchdog driver.

Cache Handling

The PNX8330 has an 8K data cache and a 16k instruction cache, which are automatically initialized and enabled by the eCos startup code. All the standard cache control macros are supported through the cache instruction. However, since all memory is always available both cached and uncached as part of the architecture, these are not always necessary.

Profiling Support

The PNX8330 HAL provides a profiling timer for use with the gprof profiling package. This uses the PNX8330 configuration timer 0, so application code should not manipulate this timer if profiling is enabled. The MIPS architectural HAL implements the mcount function so profiling is fully supported on all PNX8330-based platforms.

Other Issues

The macro HAL_PLATFORM_RESET is implemented via the PNX8330's system reset unit, and involves a full reset of the core and all peripherals. Hence, whenever a soft reset is performed by the application or via a gdb command, the system should start up again in a clean state, and there is no need for the system to reinitialize all the peripherals.

The PNX8330 HAL does not affect the implementation of data types, stack size definitions, bit indexing, idle thread processing, SMP support, system startup, or debug support.

Other Functionality

The PNX8330 processor HAL only implements functionality defined in the eCos HAL specification and does not export any additional functions.