— eCos Support for the NXP PNX8310 Processor
The NXP PNX8310 processor is based around a PR1910 MIPS core,
complemented by a range of on-chip peripherals. The HAL package
CYGPKG_HAL_MIPS_PNX8310 provides the
processor-specific support, combining the functionality of an eCos
variant HAL and processor HAL. It complements the MIPS architectural
CYGPKG_HAL_MIPS, and the PNX83xx
contains support for features common to several members of the PNX83xx
family. An eCos configuration should also include a platform HAL
support board-level details like the memory chips and off-chip
The PNX8310 HAL package should be loaded automatically when eCos is configured for appropriate target hardware. It should never be necessary to load this package explicitly. Unloading the package should only happen as a side effect of switching target hardware. The package does not contain any user-settable options.
The HAL Port
This section describes how the PNX8310 HAL package implements parts of the eCos HAL specification. It should be read in conjunction with similar sections from the architectural and variant HAL documentation.
The header file
cyg/hal/var_io.h provides definitions of
all on-chip peripherals, except for some UART definitions which are
provided by the PNX83xx support HAL instead. This header file is
automatically included by the architectural header
cyg/hal/hal_io.h, so typically
application code and other packages will just include the latter.
The register addresses are all in kseg1 so will be accessed uncached.
The header file
cyg/hal/var_intr.h provides ISR vector
numbers for all interrupt sources, for example
CYGNUM_HAL_ISR_PIO_1. These vector numbers should
be used for calls like
header file is automatically included by the architectural header
cyg/hal/hal_intr.h, and other
packages and application code will normally just include the latter.
The interrupt vectors come in three groups. There are three vectors
for the timers implemented by the PR1910 core's coprocessor 0. There
are 20 vectors for the other on-chip peripherals, managed by the
priority interrupt controller. One of these,
CYGNUM_HAL_ISR_PIO is reserved for use by the HAL's
interrupt decoding code to detect PIO interrupts. Finally there are 16
vectors for interrupts on the PIO pins.
The eCos HAL macros
HAL_INTERRUPT_SET_LEVEL are implemented by the
processor HAL. The implementations depend on the interrupt vector.
HAL_INTERRUPT_ACKNOWLEDGE is only needed for PIO
interrupts, otherwise it is a no-op.
HAL_INTERRUPT_CONFIGURE is also only relevant for
Interrupt priorities should be in the range 1 to 14, and correspond to
int_priority fields in the
pic_int_reg registers. 1 is the lowest
priority and 14 the highest. Interrupt priorities are ignored for the
three timer interrupts. All PIO interrupt sources operate at the same
priority, which is the highest priority assigned to any of the PIO
Interrupt chaining via the common HAL's configuration option
CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN is supported for
PIO interrupts only. This makes it possible to connect several
external peripherals' interrupt lines to a single PIO pin if desired.
The PR1910 core provides three timers, TMR1, TMR2 and TMR3. TMR1 is used for the eCos system clock. TMR2 is used for gprof-based profiling if enabled, otherwise it can be used by the application. TMR3 is normally used only for the watchdog device driver.
The PNX8310 has an 8K unified cache, which is automatically
initialized and enabled by the eCos startup code. The standard macros
HAL_UCACHE_SYNC are supported, and both the
DCACHE and ICACHE variants are just mapped on to these. Working
ENABLE, DISABLE and IS_ENABLED macros are provided as well but these
are not generally useful on a MIPS processor.
The PNX8310 HAL provides a profiling timer for use with the gprof
profiling package. This uses the PR1910 coprocessor 0 timer TMR2, so
application code should not manipulate this timer if profiling is
enabled. The MIPS architectural HAL implements the
mcount function so profiling is fully supported
on all PNX8310-based platforms.
HAL_PLATFORM_RESET is implemented via the
PNX8310's system reset unit, and involves a full reset of the core and
all peripherals. Hence, whenever a soft reset is performed by the
application or via a gdb command, the system should start up again in a
clean state, and there is no need for the system to reinitialize all
The PNX8310 HAL does not affect the implementation of data types, stack size definitions, bit indexing, idle thread processing, SMP support, system startup, or debug support.
The PNX8310 processor HAL only implements functionality defined in the eCos HAL specification and does not export any additional functions.
|2021-09-02||eCosPro Non-Commercial Public License|