Overview — eCos Support for the M68K Family of Processors


The original Motorola 68000 processor was released in 1979, and featured the following:

  • Eight general purpose 32-bit data registers, %D0 to %D7. Seven 32-bit address registers %A0 to %A6, with %A7 dedicated as the stack pointer. A 16-bit status register.
  • A linear address space, limited to 24-bits because the chip package only had 24 address pins. Hence the processor could address 16 megabytes of memory.
  • No separate address space for I/O operations. Instead devices are accessed just like memory via the main address and data buses.
  • 16-bit external data bus, even though the data registers were 32 bits wide.
  • A CISC variable-length instruction set with no less than 14 different addressing modes (although of course the terms RISC and CISC were not yet in common use).
  • Separate supervisor and user modes. The processor actually has two distinct stack pointer registers %A7, and the mode determines which one gets used.
  • An interrupt subsystem with support for vectored and prioritized interrupts.

The 68000 processor was used in several microcomputers of its time, including the original Apple Macintosh, the Commodore Amiga, and the Atari ST. Over the years numerous variants have been developed. The core instruction set has remained essentially unchanged. Some of the variants have additional instructions. The development of MMUs led to changes in exception handling. In more recent variants, notably the Freescale ColdFire family, some infrequently used instructions and addressing modes have been removed.

  • The 68008 reduced the widths of the external data and address buses to 8 bits and 20 bits respectively, giving the processor slow access to only one megabyte.
  • The 68010 (1982) added virtual memory support.
  • In the 68020 (1984) both the address and data buses were made 32-bits wide. A 256-byte instruction cache was added, as were some new instructions and addressing modes.
  • The 68030 (1987) included an on-chip mmu and a 256-byte data cache.
  • The 68040 (1991) added hardware floating point (previous processors relied on an external coprocessor or on software emulation). It also had larger caches and an improved mmu.
  • The 68060 (1994) involved an internally very different superscalar implementation of the architecture, but few changes at the interface level. It also contained support for power management.
  • There have been numerous 683xx variants for embedded use, with on-chip peripherals like UARTs and timers. The cpu core of these variants is also known as cpu32.
  • The MCFxxxx ColdFire series (1995) resembles a stripped-down 68060, with some instructions and addressing modes removed to allow for a much smaller and more efficient implementation. Various hardware units such as the and FPU and MMU have become optional.

eCos only provides support for some of these variants, although it should be possible to add support for additional variants with few or no changes to the architectural HAL package.

The architectural HAL provides support for those features which are common to all members of the 68000 and ColdFire families, and for certain features which are present on some but not all members. A typical eCos configuration will also contain: a variant HAL package with support code for a family of processors, for example MCFxxxx; possibly a processor HAL package with support for one specific processor, for example the MCF5272; and a platform HAL which contains the code needed for a specific hardware platform such as the m5272c3.