| The HAL Port | ||
|---|---|---|
 | Chapter 328. Freescale M5282LITE Board Support |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the M5282LITE hardware, and should be read in conjunction with that specification. The M5282LITE platform HAL package complements the M68K architectural HAL, the MCFxxxx variant HAL, and the MCF5282 processor HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset the HAL will initialize or
reinitialize most of the on-chip peripherals. There is an exception
for RAM startup applications which depend on a ROM monitor for certain
services: the UARTs and the ethernet device will not be reinitialized
because they may be in use by RedBoot for communication with the host.
Full details of this initialization can be found in the function
hal_m68k_m5282lite_init in
platform.c.
For a ROM startup the HAL will perform additional initialization,
setting up the external DRAM and chip selects. Full details can be
found in the exported header cyg/hal/plf.inc.
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- External SDRAM
- This is mapped to location 0x00000000. Most of the first kilobyte is used for hardware exception vectors. The eCos virtual vectors are also placed here, allowing RAM-based applications to use services provided by the ROM monitor. For ROM startup all remaining SDRAM is available. For RAM and DBUG startup available SDRAM starts at location 0x00010000, with the bottom 64K reserved for use by either the RedBoot or dBUG ROM monitors.
- Internal RAM
- The 64K of internal RAM are normally mapped at location 0x20000000. Neither eCos nor RedBoot use the internal RAM so all of it is available to application code.
- On-chip Peripherals
These are accessible at location 0x40000000 onwards, as per the defined symbol
HAL_MCF5282_ISPBAR.![[Note]](pix/note.png)
Note On some other coldfire processors the equivalent register is known as
%mbar. The symbolHAL_MCFxxxx_MBARis an alias forHAL_MCF5282_ISPBAR, making it easier to share device drivers.- On-chip Flash
- The 512K of internal flash are normally mapped at location 0xF0000000. Currently this is not used by eCos or RedBoot.
- External Flash
- This is located at the top of memory, location 0xFFE00000 onwards. In a typical setup the first two 64K flash blocks at location 0xFFE00000 are used to hold RedBoot, and the last flash block at location 0xFFFF0000 is used to hold flash management data and the RedBoot fconfig variables. The remaining blocks can be used by application code.
Clock Support
The platform HAL provides configuration options for the eCos system clock. This always uses the hardware timer PIT3, which should not be used directly by application code. The actual HAL macros for managing the clock are provided by the MCF5282 processor HAL. The specific numbers used are a characteristic of the platform because they depend on the processor speed. The gprof-based profiling code uses PIT2. Timers PIT0 and PIT1 are not used by eCos so application code is free to manipulate these as required.
Other Issues
The M5282LITE platform HAL does not affect the implementation of other parts of the eCos HAL specification. The MCF5282 processor HAL, the MCFxxxx variant HAL, and the M68K architectural HAL documentation should be consulted for further details.
Other Functionality
The platform HAL package also provides a flash driver for the off-chip
ST M29W160EB flash chip or compatible. This driver is inactive by
default, and only becomes active if the configuration includes the
generic flash support CYGPKG_IO_FLASH.
| |  | |
| Configuration |  | Chapter 329. SSV DNP/5280 Board Support |
| 2024-12-10 | eCosPro Non-Commercial Public License |