On-chip Subsystems and Peripherals
Prev Chapter 353. MPC512X Variant Support Next

Name

On-chip Subsystems and Peripherals — Hardware Support

Hardware support

This section describes the devices controlled by this HAL.

Cache Handling

The MPC512X contains both data and instruction caches. The cyg/hal/hal_cache.h header defines the cache sizes for the processor variants and defines the eCos standard macros for operating on the caches.

PSC support

The MPC512X contains a number of general purpose Programmable Serial Controllers (PSCs) which can be used as UARTs or SPI master or slave controllers (along with other modes that eCos does not support).

For each PSC, N, there are a number of configuration options:

CYGHWR_HAL_POWERPC_MPC512X_PSCN
This defines the mode in which this PSC is to be used. If set to UNUSED then the PSC is not used and its external pins are available for alternate device functions. If it is set to UART it is used as a UART. If set to SPI then it is an SPI master, and if set to SPISLAVE an SPI slave device.
CYGHWR_HAL_POWERPC_MPC512X_PSCN_TXFIFO_SIZE
This defines the size of the transmit FIFO for this PSC, and must be a multiple of 4. The default value is chosen depending on the mode.
CYGHWR_HAL_POWERPC_MPC512X_PSCN_RXFIFO_SIZE
This defines the size of the receive FIFO for this PSC, and must be a multiple of 4. The default value is chosen depending on the mode.
CYGHWR_HAL_POWERPC_MPC512X_PSCN_TXFIFO_ADDRESS
This defines the address in the shared FIFO RAM of the transmit FIFO for this PSC. This value is usually calculated from the defined sizes of the PSCs and should not be changed without good reason.
CYGHWR_HAL_POWERPC_MPC512X_PSCN_RXFIFO_ADDRESS
This defines the address in the shared FIFO RAM of the transmit FIFO for this PSC. This value is usually calculated from the defined sizes of the PSCs and should not be changed without good reason.

It is normally the responsibility of the platform HAL to define the mode in which each PSC is to be used.

The MPC512X variant HAL supports basic polled HAL diagnostic I/O over any of the PSC UART devices. There is also a fully interrupt-driven serial device driver suitable for eCos applications for all on-chip serial devices. The serial driver consists of an eCos package: CYGPKG_IO_SERIAL_POWERPC_PSC which provides all support for the MPC512X PSC serial devices. Using the HAL diagnostic I/O support, any of these devices can be used by the ROM monitor or RedBoot for communication with GDB. If a device is needed by the application, either directly or via the serial driver, then it cannot also be used for GDB communication using the HAL I/O support. An alternative serial port should be used instead.

Any PSC which is put into UART mode will be included in both the HAL's list of available polled serial devices and be available for use by the serial driver. The MPC512X UARTs provide TX and RX data lines plus hardware flow control using RTS/CTS for those UARTs that have them connected.

A separate SPI master driver is available as the package CYGPKG_DEVS_SPI_POWERPC_PSC, and SPI slave support is present in this variant HAL and is described later.

Interrupts

The MPC512X HAL provides standard support for interrupt decoding and delivery. The available interrupt vectors are defined in the cyg/hal/hal_intr.h header. Interrupts from the FIFO controller are additionally decoded into their own separate set of vectors.

The MPC512X has a somewhat unusual interrupt priority mechanism. Vectors are collected together into groups and the priority of an interrupt can only be varied within that group. The unusual part is that instead of assigning a priority to a vector, a vector is assigned to a priority. It is not permitted to assign a vector to more than one priority. eCos does not enforce unique priority assignments, this is left to the user. Priorities range from 0 to 7; any value outside that range will leave the priority unchanged at the hardware default. Hence in many placed, a priority value of 8 is used to effectively not change the setting.

GPIO and Pin Configuration

The variant HAL provides support for packaging the configuration of a GPIO line into a single 16-bit descriptor that can then be used with macros to configure the pin and set and read its value. Similar descriptor based support is also available for controlling the configuration of external IO pins.

I²C Support

This variant HAL contains an I²C driver that may be used with the standard I²C infrastructure. For each I²C bus there are a number of configuration options:

CYGINT_HAL_POWERPC_MPC512X_I2C_BUSN
This interface must be implemented by the platform HAL to indicate that the given I²C bus is connected to devices.
CYGHWR_HAL_POWERPC_MPC512X_I2C_BUSN_CLOCK
This is the I²C bus clock speed in Hz. Usually frequencies of either 100kHz or 400kHz are chosen, the latter sometimes known as fast mode.
CYGHWR_HAL_POWERPC_MPC512X_I2C_BUSN_INTR_PRI
This is the I²C bus interrupt priority. It may range from 0 to 7; the default of 8 selects the default hardware setting.

Profiling Support

The MPC512X HAL contains support for gprof-base profiling using a sampling timer. The default timer used is GPT7. The timer used is selected by a set of #defines in src/var_misc.c which can be changed to refer to a different timer if required. This timer is only enabled when the gprof profiling package (CYGPKG_PROFILE_GPROF) is included and enabled in the eCos configuration, otherwise it remains available for application use.

Clock Control

The platform HAL must provide the input clock frequency (CYGHWR_HAL_POWERPC_MPC512X_CLOCK_REF_CLK) in its CDL file. This is then combined with the following options defined in this package to calculate the system clocks:

CYGHWR_HAL_POWERPC_MPC512X_CLOCK_SPMF
This defines the system PLL multiplier and should match the value supplied by the reset configuration word.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_SYS_DIV
This option defines the system clock divider multiplied by 10. It must match the value supplied by the reset configuration word. CDL does not currently handle real values, so this value must be represented by a scaled integer. Not all values that can be represented by this option are valid.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_CPMF
This option defines the Core PLL multiplier multiplied by 10. It must match the value supplied by the reset configuration word. CDL does not currently handle real values, so this value must be represented by a scaled integer.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_SDHC_DIV
This option defines the SDHC divider multiplied by 100. It must match the value programmed into the SCFR2 register by the platform HAL initialization code. The default value equates to the hardware default setting for the register. CDL does not currently handle real values, so this value must be represented by a scaled integer. Not all values that can be represented by this option are valid.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_DIU_DIV
This option defines the DIU divider multiplied by 100. It must match the value programmed into the SCFR1 register by the platform HAL initialization code. The default value equates to the hardware default setting for the register. CDL does not currently handle real values, so this value must be represented by a scaled integer. Not all values that can be represented by this option are valid.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_IPS_DIV
This option defines the IPS divider. It must match the value programmed into the SCFR1 register by the platform HAL initialization code. The default value equates to the hardware default setting for the register.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_PCI_DIV
This option defines the PCI divider. It must match the value programmed into the SCFR1 register by the platform HAL initialization code. The default value equates to the hardware default setting for the register.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_LPC_DIV
This option defines the LPC divider. It must match the value programmed into the SCFR1 register by the platform HAL initialization code. The default value equates to the hardware default setting for the register.
CYGHWR_HAL_POWERPC_MPC512X_CLOCK_NFC_DIV
This option defines the NFC divider. It must match the value programmed into the SCFR1 register by the platform HAL initialization code. The default value equates to the hardware default setting for the register.

These setting are used to calculate a variety of clock values which are then used in the HALs and drivers to set baud rates, timers and other clock-related features.

Note that when changing or configuring any of these clock settings, you should consult the relevant processor datasheet as there may be both upper and lower constraints on the frequencies of some clock signals, including intermediate clocks. There are also some clocks where, while there is no strict constraint, clock stability is improved if values are chosen wisely. Finally, be aware that increasing clock speeds using this package may have an effect on platform specific properties, such as memory timings which may have to be adjusted accordingly.

Prev Up Next
MPC512X Variant HAL Home SPI Slave support