I2C Two Wire Interface
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Name

I2C Two Wire Interface — Using I²C devices

Overview

The I²C driver in the OMAP processor HAL supports the use of I²C devices within eCos. Access to the driver will be via the standard I²C interface subsystem.

This driver provides support for both I²C busses available on the OMAP L1XX.

Configuration

The HAL contains the following configuration options for the two I²C busses:

CYGINT_HAL_ARM_ARM9_OMAP_L1XX_I2C_BUSX
This interface controls the inclusion of support for I²C bus X. This will normally be implemented by the platform HAL to indicate that there are I²C devices attached to the given bus, or that the SCL and SDA lines are routed to an external connector.
CYGNUM_HAL_ARM_ARM9_OMAP_L1XX_I2C_BUSX_CLOCK
This is the I²C bus X clock speed in Hz. Usually frequencies of either 100kHz or 400kHz are chosen, the latter sometimes known as fast mode.
CYGNUM_HAL_ARM_ARM9_OMAP_L1XX_I2C_BUSX_INTR_PRI
This is the I²C bus X interrupt priority. It may range from 1 to 29; the default of 15 places it in the centre of the priority range.

Additionally the HAL contains the following configuration option which applies to both I²C buses:

CYGNUM_HAL_ARM_ARM9_OMAP_L1XX_I2C_ALIGNED_RXBUF_SIZE
When using DMA, transferred received data buffers must be aligned to the data cache line size, and its size must be a multiple of the cache line size. If the user does not pass in a suitable buffer, a bounce buffer must be used for the entire transfer. This option provides the size of that buffer. You should set this buffer to the maximum amount of data you can receive in a single transfer. If you can guarantee that all uses of this I²C driver use appropriately aligned receive buffers, then you can disable this option entirely in order to remove the buffer. It defaults to 1024 bytes per I²C bus.

Usage Notes

The design of the OMAP L1XX I²C device does not make it possible to start a new bus transfer without also sending a START condition on the bus. This means that divided transactions are not possible. A divided transaction would look like this: 

    cyg_i2c_transaction_begin(&cyg_aardvark_at24c02);
    cyg_i2c_transaction_tx(&cyg_aardvark_at24c02, 1, tx_buf1, 1, 0);
    cyg_i2c_transaction_tx(&cyg_aardvark_at24c02, 0, tx_buf2, 2, 0);
    cyg_i2c_transaction_tx(&cyg_aardvark_at24c02, 0, tx_buf3, 6, 1);
    cyg_i2c_transaction_end(&cyg_aardvark_at24c02);

In this transaction a START and one byte are sent from tx_buf1, then 2 bytes of data from tx_buf2, finishing with 6 bytes from tx_buf3 followed by a STOP. The OMAP L1XX will not allow the tx_buf2 and tx_buf3 transfers to happen without also sending a START. The only solution to this is to combine the data into a single buffer and perform a single transfer: 

    memcpy( tx_buf, tx_buf1, 1);
    memcpy( tx_buf+1, tx_buf2, 2);
    memcpy( tx_buf+3, tx_buf3, 6);
    cyg_i2c_tx(&cyg_aardvark_at24c02, tx_buf, 9);
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