| The HAL Port | ||
|---|---|---|
 | Chapter 307. STM32L476-DISCO Platform HAL |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the STM32L476-DISCO board hardware, and should be read in conjunction with that specification. The STM32L476-DISCO platform HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset the HAL will initialize or
reinitialize many of the on-chip peripherals. There is an
exception for RAM startup applications which
depend on a ROM monitor for certain services.
For ROM, ROMAPP and
SRAM startup types the HAL will perform
additional initialization, programming the various internal
registers including the PLL, peripheral clocks and GPIO pins. The
details of the early hardware startup may be found in the
src/stm32l476_disco_misc.c in both
hal_system_init and
hal_platform_init.
Memory Map
The platform HAL package provides the memory layout information
needed to generate the linker script. For all the STARTUP
variations the top
CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes
of the on-chip SRAM are reserved for the interrupt stack. The
remainder of the internal SRAM is available for use by
applications. The key memory locations are as follows:
- Internal SRAM
-
This is located at address
0x20000000of the memory space, and is 192KiB in size. The eCos VSR table occupies the bottom 392 bytes of memory, with the virtual vector table starting at0x20000188and extending to0x20000288. - Internal FLASH
-
This is located at address
0x08000000of the memory space and will be mapped to0x00000000at reset. This region is 1024KiB in size.ROMandROMAPPapplications are by default configured to run from this memory. - On-Chip Peripherals
-
These are accessible at locations
0x40000000and0xE0000000upwards. Descriptions of the contents can be found in the STM32 User Manual.
Linker Scripts
The platform linker scripts define the following symbols:
- hal_vsr_table
-
This defines the location of the VSR table. This is set to
0x20000000for all startup types, and space for 98 entries is reserved. - hal_virtual_vector_table
-
This defines the location of the virtual vector table used to
communicate between an ROM monitor and an eCos
application. This is allocated right after the VSR table, at
0x20000188. - hal_interrupt_stack
-
This defines the location of the interrupt stack. This is
allocated to the top of internal SRAM, from
0x20018000down. - hal_startup_stack
- This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.
Flash wait states
The STM32L476-DISCO platform HAL provides a configuration option
to set the number of Flash read wait states to use:
CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It
is important to verify and if necessary update this value if
changing the CPU clock (HCLK) frequency or CPU voltage. Consult
the relevant STM32 datasheets and programming manuals for the
STM32L476 parts for appropriate values for different clock speeds
or voltages. The default of 4 reflects a supply voltage in Vcore
range 1 and HCLK of 80MHz.
Real-time characterization
The tm_basic kernel test gives statistics
gathered about the real-time characterization and performance of
the kernel. The sample output is shown here for information. The
test was built for SRAM startup with
optimization flag -O2, since it provides the best performance as
both code and data could remain on-chip.
Example 307.1. stm32l476_disco Real-time characterization
Startup, main thrd : stack used 360 size 1536
Startup : Idlethread stack used 76 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 13.03 microseconds (13 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 16
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1088
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
INFO:<Ctrl-C disabled until test completion>
7.13 6.00 8.00 0.66 37% 25% Create thread
2.00 2.00 2.00 0.00 100% 100% Yield thread [all suspended]
1.88 1.00 2.00 0.22 87% 12% Suspend [suspended] thread
1.69 1.00 2.00 0.43 68% 31% Resume thread
2.50 2.00 4.00 0.56 93% 56% Set priority
0.38 0.00 1.00 0.47 62% 62% Get priority
4.63 4.00 7.00 0.63 93% 50% Kill [suspended] thread
1.63 1.00 2.00 0.47 62% 37% Yield [no other] thread
2.56 2.00 3.00 0.49 56% 43% Resume [suspended low prio] thread
2.06 2.00 3.00 0.12 93% 93% Resume [runnable low prio] thread
2.19 2.00 3.00 0.30 81% 81% Suspend [runnable] thread
2.00 2.00 2.00 0.00 100% 100% Yield [only low prio] thread
1.50 1.00 2.00 0.50 100% 50% Suspend [runnable->not runnable]
4.50 4.00 6.00 0.56 93% 56% Kill [runnable] thread
3.88 3.00 5.00 0.33 75% 18% Destroy [dead] thread
8.31 8.00 10.00 0.47 75% 75% Destroy [runnable] thread
9.88 9.00 12.00 0.55 56% 31% Resume [high priority] thread
3.02 3.00 5.00 0.03 99% 99% Thread switch
0.36 0.00 1.00 0.46 64% 64% Scheduler lock
1.49 1.00 2.00 0.50 50% 50% Scheduler unlock [0 threads]
1.52 1.00 2.00 0.50 51% 48% Scheduler unlock [1 suspended]
1.41 1.00 2.00 0.48 59% 59% Scheduler unlock [many suspended]
1.42 1.00 2.00 0.49 57% 57% Scheduler unlock [many low prio]
0.41 0.00 1.00 0.48 59% 59% Init mutex
1.97 1.00 2.00 0.06 96% 3% Lock [unlocked] mutex
2.03 2.00 3.00 0.06 96% 96% Unlock [locked] mutex
1.78 1.00 2.00 0.34 78% 21% Trylock [unlocked] mutex
1.66 1.00 2.00 0.45 65% 34% Trylock [locked] mutex
0.53 0.00 1.00 0.50 53% 46% Destroy mutex
12.09 12.00 13.00 0.17 90% 90% Unlock/Lock mutex
1.00 1.00 1.00 0.00 100% 100% Create mbox
0.34 0.00 1.00 0.45 65% 65% Peek [empty] mbox
2.03 2.00 3.00 0.06 96% 96% Put [first] mbox
0.38 0.00 1.00 0.47 62% 62% Peek [1 msg] mbox
2.03 2.00 3.00 0.06 96% 96% Put [second] mbox
0.31 0.00 1.00 0.43 68% 68% Peek [2 msgs] mbox
1.94 1.00 3.00 0.18 87% 9% Get [first] mbox
1.91 1.00 2.00 0.17 90% 9% Get [second] mbox
1.75 1.00 2.00 0.38 75% 25% Tryput [first] mbox
1.69 1.00 2.00 0.43 68% 31% Peek item [non-empty] mbox
1.81 1.00 2.00 0.31 81% 18% Tryget [non-empty] mbox
1.75 1.00 2.00 0.38 75% 25% Peek item [empty] mbox
1.72 1.00 3.00 0.45 65% 31% Tryget [empty] mbox
0.34 0.00 1.00 0.45 65% 65% Waiting to get mbox
0.38 0.00 1.00 0.47 62% 62% Waiting to put mbox
0.63 0.00 1.00 0.47 62% 37% Delete mbox
8.78 8.00 9.00 0.34 78% 21% Put/Get mbox
0.38 0.00 1.00 0.47 62% 62% Init semaphore
1.59 1.00 2.00 0.48 59% 40% Post [0] semaphore
1.81 1.00 2.00 0.31 81% 18% Wait [1] semaphore
1.50 1.00 2.00 0.50 100% 50% Trywait [0] semaphore
1.59 1.00 2.00 0.48 59% 40% Trywait [1] semaphore
0.50 0.00 1.00 0.50 100% 50% Peek semaphore
0.50 0.00 1.00 0.50 100% 50% Destroy semaphore
7.63 7.00 8.00 0.47 62% 37% Post/Wait semaphore
0.81 0.00 1.00 0.31 81% 18% Create counter
0.59 0.00 1.00 0.48 59% 40% Get counter value
0.44 0.00 1.00 0.49 56% 56% Set counter value
2.00 2.00 2.00 0.00 100% 100% Tick counter
0.44 0.00 1.00 0.49 56% 56% Delete counter
0.41 0.00 1.00 0.48 59% 59% Init flag
1.72 1.00 3.00 0.45 65% 31% Destroy flag
1.53 1.00 2.00 0.50 53% 46% Mask bits in flag
1.84 1.00 3.00 0.32 78% 18% Set bits in flag [no waiters]
2.44 2.00 3.00 0.49 56% 56% Wait for flag [AND]
2.41 2.00 3.00 0.48 59% 59% Wait for flag [OR]
2.53 2.00 4.00 0.53 96% 50% Wait for flag [AND/CLR]
2.50 2.00 3.00 0.50 100% 50% Wait for flag [OR/CLR]
0.38 0.00 1.00 0.47 62% 62% Peek on flag
1.22 1.00 2.00 0.34 78% 78% Create alarm
2.63 2.00 3.00 0.47 62% 37% Initialize alarm
1.53 1.00 2.00 0.50 53% 46% Disable alarm
2.59 2.00 4.00 0.52 53% 43% Enable alarm
1.69 1.00 2.00 0.43 68% 31% Delete alarm
2.16 2.00 3.00 0.26 84% 84% Tick counter [1 alarm]
10.34 10.00 11.00 0.45 65% 65% Tick counter [many alarms]
3.50 3.00 5.00 0.53 96% 53% Tick & fire counter [1 alarm]
51.81 51.00 53.00 0.36 75% 21% Tick & fire counters [>1 together]
11.69 11.00 12.00 0.43 68% 31% Tick & fire counters [>1 separately]
12.00 12.00 12.00 0.00 100% 100% Alarm latency [0 threads]
10.06 10.00 12.00 0.12 95% 95% Alarm latency [2 threads]
11.20 10.00 12.00 0.52 54% 12% Alarm latency [many threads]
18.02 18.00 20.00 0.03 99% 99% Alarm -> thread resume latency
1.00 1.00 1.00 0.00 Clock/interrupt latency
4.96 4.00 6.00 0.00 Clock DSR latency
181 152 212 Worker thread stack used (stack size 1088)
All done, main thrd : stack used 796 size 1536
All done : Idlethread stack used 164 size 1280
Timing complete - 29810 ms total
PASS:<Basic timing OK>
EXIT:<done>| |  | |
| Hardware debugging support |  | Test Programs |
| 2024-03-18 | eCosPro Non-Commercial Public License |