The HAL Port

The HAL Port
	Chapter 306. STM32F7XX-EVAL Platform HAL

Overview

This documentation explains how the eCos HAL specification has been mapped onto the STM32F7XX-EVAL board hardware, and should be read in conjunction with that specification. The STM32F7XX-EVAL platform HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset the HAL will initialize or reinitialize many of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM, ROMINT, SRAM, JTAG and SRAMEXT startup types the HAL will perform additional initialization, programming the various internal registers including the PLL, peripheral clocks and GPIO pins. The details of the early hardware startup may be found in the src/stm32f7xx_eval_misc.c in both hal_system_init and hal_platform_init.

Memory Map

The platform HAL package provides the memory layout information needed to generate the linker script. For all the STARTUP variations the top CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes of the on-chip SRAM are reserved for the interrupt stack. The remainder of the internal SRAM is available for use by applications. The key memory locations are as follows:

Internal RAM

This is located at address 0x20000000 of the memory space, and is 320KiB in size. The eCos VSR table occupies the bottom 392 bytes of memory, with the virtual vector table starting at 0x200001AC and extending to 0x200002AC.

This memory region comprises three contiguous memory blocks, the DTCM (Data Tightly Coupled Memory), SRAM region 1 and SRAM region 2.

External SDRAM

This is located at address 0x60000000 of the memory space, and is 32MiB long. For ROM applications, all of the SDRAM is available for use. For JTAG applications the application is loaded from 0x80000000 with the remaining SDRAM after the code+data available for application use.

For RAM startup applications, SDRAM below 0x60008000 is reserved for the debug monitor (e.g. RedBoot).

External SRAM

This is located at address 0x64000000 of the memory space, and is 2MiB long. For SRAMEXT applications, all of the external SRAM is available for use.

Internal FLASH

This is located at address 0x08000000 of the memory space and will be mapped to 0x00000000 at reset. This region is 1024KiB in size. ROM and ROMINT applications are by default configured to run from this memory.

External FLASH

This is located at address 0xC0000000 of the memory space. This region is 16MiB in size.

On-Chip Peripherals

These are accessible at locations 0x40000000 and 0xE0000000 upwards. Descriptions of the contents can be found in the STM32 User Manual.

Linker Scripts

The platform linker scripts define the following symbols:

hal_vsr_table: This defines the location of the VSR table. This is set to 0x20000000 for all startup types, and space for 98 entries is reserved.
hal_virtual_vector_table: This defines the location of the virtual vector table used to communicate between an ROM monitor and an eCos application. This is allocated right after the VSR table, at 0x200001AC.
hal_interrupt_stack: This defines the location of the interrupt stack. This is allocated to the top of internal SRAM, 0x20030000.
hal_startup_stack: This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.

Diagnostic LEDs

Four LEDs are fitted on the board for diagnostic purposes and are labelled LD1 (green), LD2 (orange), LD3 (red) and LD4 (blue).

The platform HAL header file at <cyg/hal/plf_io.h> defines the following convenience function to allow LEDs LD1 and LD3 to be set:

extern void hal_stm32f7xx_eval_led(char c);

However, LEDs LD2 and LD4 cannot be set with this function as it is intended for low level control of the LEDs, but LD2 and LD4 are under MFX_GPO control. This means setting them would result in I²C transactions which in turn means the function could not be called from ISR/DSR or system-critical code.

Nevertheless, the lowest 4-bits of the argument c correspond to the LED number (with LED0/LD1 as the least significant bit). Attempting to set the bits for LD2/LD4 will have no effect.

Table 306.1. LEDs

eCos LED GPIO manifest	STM32F7 GPIO	Bit number	Board label	Colour
`CYGHWR_HAL_STM32F7XX_EVAL_LED0`	`PF10`	`0`	`LD1`	Green
`CYGHWR_HAL_STM32F7XX_EVAL_LED2`	`PB7`	`2`	`LD3`	Red

The platform HAL will automatically light LED0 when the platform initialisation is complete, however the LEDs are then free for application use.

Flash wait states

The STM32F7XX-EVAL platform HAL provides a configuration option to set the number of Flash read wait states to use: CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It is important to verify and if necessary update this value if changing the CPU clock (HCLK) frequency or CPU voltage. Consult the STM32 Flash programming manual (PM0081) for appropriate values for different clock speeds or voltages. The default of 5 reflects a supply voltage of 3.3V and HCLK of 168MHz.

Real-time characterization

The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built for SRAM startup with optimization flag -O2, since it provides the best performance as both code and data could remain on-chip.

Example 306.1. stm32f7xx_eval Real-time characterization

             Startup, main thrd : stack used   352 size  1536
             Startup : Idlethread stack used    76 size  1280

eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated

Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took    3.13 microseconds (3 raw clock ticks)

Testing parameters:
   Clock samples:            32
   Threads:                  16
   Thread switches:         128
   Mutexes:                  32
   Mailboxes:                32
   Semaphores:               32
   Scheduler operations:    128
   Counters:                 32
   Flags:                    32
   Alarms:                   32
   Stack Size:             1088


                                 Confidence
     Ave     Min     Max     Var  Ave  Min  Function
  ======  ======  ======  ====== ========== ========
    2.00    1.00    3.00    0.13   87%   6% Create thread
    0.44    0.00    1.00    0.49   56%  56% Yield thread [all suspended]
    0.56    0.00    1.00    0.49   56%  43% Suspend [suspended] thread
    0.50    0.00    1.00    0.50  100%  50% Resume thread
    0.69    0.00    1.00    0.43   68%  31% Set priority
    0.25    0.00    1.00    0.38   75%  75% Get priority
    1.19    1.00    2.00    0.30   81%  81% Kill [suspended] thread
    0.44    0.00    1.00    0.49   56%  56% Yield [no other] thread
    0.69    0.00    1.00    0.43   68%  31% Resume [suspended low prio] thread
    0.50    0.00    1.00    0.50  100%  50% Resume [runnable low prio] thread
    0.56    0.00    1.00    0.49   56%  43% Suspend [runnable] thread
    0.44    0.00    1.00    0.49   56%  56% Yield [only low prio] thread
    0.44    0.00    1.00    0.49   56%  56% Suspend [runnable->not runnable]
    1.25    1.00    2.00    0.38   75%  75% Kill [runnable] thread
    1.13    1.00    2.00    0.22   87%  87% Destroy [dead] thread
    2.19    2.00    3.00    0.30   81%  81% Destroy [runnable] thread
    2.88    2.00    4.00    0.44   62%  25% Resume [high priority] thread
    0.80    0.00    2.00    0.33   78%  20% Thread switch

    0.12    0.00    1.00    0.21   88%  88% Scheduler lock
    0.36    0.00    1.00    0.46   64%  64% Scheduler unlock [0 threads]
    0.33    0.00    1.00    0.44   67%  67% Scheduler unlock [1 suspended]
    0.40    0.00    1.00    0.48   60%  60% Scheduler unlock [many suspended]
    0.33    0.00    1.00    0.44   67%  67% Scheduler unlock [many low prio]

    0.16    0.00    1.00    0.26   84%  84% Init mutex
    0.53    0.00    1.00    0.50   53%  46% Lock [unlocked] mutex
    0.50    0.00    1.00    0.50  100%  50% Unlock [locked] mutex
    0.47    0.00    1.00    0.50   53%  53% Trylock [unlocked] mutex
    0.38    0.00    1.00    0.47   62%  62% Trylock [locked] mutex
    0.22    0.00    1.00    0.34   78%  78% Destroy mutex
    3.69    3.00    4.00    0.43   68%  31% Unlock/Lock mutex

    0.28    0.00    1.00    0.40   71%  71% Create mbox
    0.16    0.00    1.00    0.26   84%  84% Peek [empty] mbox
    0.56    0.00    1.00    0.49   56%  43% Put [first] mbox
    0.16    0.00    1.00    0.26   84%  84% Peek [1 msg] mbox
    0.59    0.00    1.00    0.48   59%  40% Put [second] mbox
    0.19    0.00    1.00    0.30   81%  81% Peek [2 msgs] mbox
    0.50    0.00    1.00    0.50  100%  50% Get [first] mbox
    0.44    0.00    1.00    0.49   56%  56% Get [second] mbox
    0.47    0.00    1.00    0.50   53%  53% Tryput [first] mbox
    0.47    0.00    1.00    0.50   53%  53% Peek item [non-empty] mbox
    0.56    0.00    1.00    0.49   56%  43% Tryget [non-empty] mbox
    0.44    0.00    1.00    0.49   56%  56% Peek item [empty] mbox
    0.44    0.00    1.00    0.49   56%  56% Tryget [empty] mbox
    0.13    0.00    1.00    0.22   87%  87% Waiting to get mbox
    0.13    0.00    1.00    0.22   87%  87% Waiting to put mbox
    0.28    0.00    1.00    0.40   71%  71% Delete mbox
    2.19    2.00    3.00    0.30   81%  81% Put/Get mbox

    0.13    0.00    1.00    0.22   87%  87% Init semaphore
    0.41    0.00    1.00    0.48   59%  59% Post [0] semaphore
    0.47    0.00    1.00    0.50   53%  53% Wait [1] semaphore
    0.38    0.00    1.00    0.47   62%  62% Trywait [0] semaphore
    0.41    0.00    1.00    0.48   59%  59% Trywait [1] semaphore
    0.25    0.00    1.00    0.38   75%  75% Peek semaphore
    0.16    0.00    1.00    0.26   84%  84% Destroy semaphore
    2.00    2.00    2.00    0.00  100% 100% Post/Wait semaphore

    0.19    0.00    1.00    0.30   81%  81% Create counter
    0.06    0.00    1.00    0.12   93%  93% Get counter value
    0.13    0.00    1.00    0.22   87%  87% Set counter value
    0.53    0.00    1.00    0.50   53%  46% Tick counter
    0.16    0.00    1.00    0.26   84%  84% Delete counter

    0.16    0.00    1.00    0.26   84%  84% Init flag
    0.34    0.00    1.00    0.45   65%  65% Destroy flag
    0.38    0.00    1.00    0.47   62%  62% Mask bits in flag
    0.41    0.00    1.00    0.48   59%  59% Set bits in flag [no waiters]
    0.63    0.00    1.00    0.47   62%  37% Wait for flag [AND]
    0.66    0.00    1.00    0.45   65%  34% Wait for flag [OR]
    0.69    0.00    1.00    0.43   68%  31% Wait for flag [AND/CLR]
    0.63    0.00    1.00    0.47   62%  37% Wait for flag [OR/CLR]
    0.16    0.00    1.00    0.26   84%  84% Peek on flag

    0.38    0.00    1.00    0.47   62%  62% Create alarm
    0.66    0.00    1.00    0.45   65%  34% Initialize alarm
    0.44    0.00    1.00    0.49   56%  56% Disable alarm
    0.59    0.00    1.00    0.48   59%  40% Enable alarm
    0.44    0.00    1.00    0.49   56%  56% Delete alarm
    0.69    0.00    1.00    0.43   68%  31% Tick counter [1 alarm]
    2.31    2.00    3.00    0.43   68%  68% Tick counter [many alarms]
    0.94    0.00    1.00    0.12   93%   6% Tick & fire counter [1 alarm]
   14.03   14.00   15.00    0.06   96%  96% Tick & fire counters [>1 together]
    2.69    2.00    3.00    0.43   68%  31% Tick & fire counters [>1 separately]
    3.00    3.00    3.00    0.00  100% 100% Alarm latency [0 threads]
    2.48    2.00    3.00    0.50   52%  52% Alarm latency [2 threads]
    3.00    3.00    3.00    0.00  100% 100% Alarm latency [many threads]
    4.99    4.00    5.00    0.02   99%   0% Alarm -> thread resume latency

    0.00    0.00    0.00    0.00            Clock/interrupt latency

    1.92    1.00    2.00    0.00            Clock DSR latency

     191     160     204                    Worker thread stack used (stack size 1088)
            All done, main thrd : stack used   796 size  1536
            All done : Idlethread stack used   164 size  1280

Timing complete - 29810 ms total

PASS:<Basic timing OK>
EXIT:<done>


Hardware debugging support		Test Programs

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