| The HAL Port | ||
|---|---|---|
 | Chapter 305. STM32F746G-DISCO Platform HAL |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the STM32F746G-DISCO board hardware, and should be read in conjunction with that specification. The STM32F746G-DISCO platform HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset the HAL will initialize or reinitialize
many of the on-chip peripherals. There is an exception
for RAM startup applications which depend on a ROM
monitor for certain services.
For ROM, ROMINT, SRAM
and JTAG startup types the HAL will perform
additional initialization, programming the various internal registers
including the PLL, peripheral clocks and GPIO pins. The details of the
early hardware startup may be found in
the src/stm32f746g_disco_misc.c in
both hal_system_init
and hal_platform_init.
Memory Map
The platform HAL package provides the memory layout information needed
to generate the linker script. For all the STARTUP variations the
top CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes
of the on-chip SRAM are reserved for the interrupt stack. The
remainder of the internal SRAM is available for use by
applications. The key memory locations are as follows:
- Internal RAM
This is located at address
0x20000000of the memory space, and is 320KiB in size. The eCos VSR table occupies the bottom 456-bytes of memory, with the virtual vector table starting at0x200001C8and extending to0x200002C8.This memory region comprises three contiguous memory blocks, the DTCM (Data Tightly Coupled Memory), SRAM region 1 and SRAM region 2.
- External SDRAM
This is located at address
0x60000000of the memory space, and is 8MiB long. ForROMapplications, all of the SDRAM is available for use. ForJTAGapplications the application is loaded from0x60000000with the remaining SDRAM after the code+data available for application use.For
RAMstartup applications, SDRAM below0x60008000is reserved for the debug monitor (e.g. RedBoot).- Internal FLASH
-
This is located at address
0x08000000of the memory space and will be mapped to0x00000000at reset. This region is 1024KiB in size.ROMandROMINTapplications are by default configured to run from this memory. - On-Chip Peripherals
-
These are accessible at locations
0x40000000and0xE0000000upwards. Descriptions of the contents can be found in the STM32 User Manual.
Linker Scripts
The platform linker scripts define the following symbols:
- hal_vsr_table
-
This defines the location of the VSR table. This is set
to
0x20000000for all startup types, and space for 114 entries is reserved. - hal_virtual_vector_table
-
This defines the location of the virtual vector table used to
communicate between an ROM monitor and an eCos application. This is
allocated right after the VSR table, at
0x200001C8. - hal_interrupt_stack
-
This defines the location of the interrupt stack. This is allocated to
the top of internal SRAM,
0x20050000. - hal_startup_stack
- This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.
Flash wait states
The STM32F746G-DISCO platform HAL provides a configuration option to
set the number of Flash read wait states to
use: CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It
is important to verify and if necessary update this value if changing
the CPU clock (HCLK) frequency or CPU voltage. Consult the relevant
STM32 datasheets and programming manuals for the STM32F746G parts for
appropriate values for different clock speeds or voltages. The default
of 5 reflects a supply voltage of 3.3V and HCLK of 180MHz.
Real-time characterization
The tm_basic kernel test gives statistics gathered
about the real-time characterization and performance of the
kernel. The sample output is shown here for information. The test was
built for SRAM startup with optimization flag
-O2, since it provides the best performance as both code and data
could remain on-chip.
Example 305.1. stm32f746g_disco Real-time characterization
Startup, main thrd : stack used 360 size 1536
Startup : Idlethread stack used 84 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 3.03 microseconds (3 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 16
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1088
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
INFO:<Ctrl-C disabled until test completion>
1.94 1.00 3.00 0.23 81% 12% Create thread
0.38 0.00 1.00 0.47 62% 62% Yield thread [all suspended]
0.44 0.00 1.00 0.49 56% 56% Suspend [suspended] thread
0.31 0.00 1.00 0.43 68% 68% Resume thread
0.56 0.00 1.00 0.49 56% 43% Set priority
0.13 0.00 1.00 0.22 87% 87% Get priority
1.13 1.00 2.00 0.22 87% 87% Kill [suspended] thread
0.38 0.00 1.00 0.47 62% 62% Yield [no other] thread
0.69 0.00 2.00 0.52 56% 37% Resume [suspended low prio] thread
0.44 0.00 1.00 0.49 56% 56% Resume [runnable low prio] thread
0.56 0.00 1.00 0.49 56% 43% Suspend [runnable] thread
0.44 0.00 1.00 0.49 56% 56% Yield [only low prio] thread
0.50 0.00 1.00 0.50 100% 50% Suspend [runnable->not runnable]
1.19 1.00 2.00 0.30 81% 81% Kill [runnable] thread
1.06 1.00 2.00 0.12 93% 93% Destroy [dead] thread
2.06 2.00 3.00 0.12 93% 93% Destroy [runnable] thread
2.63 2.00 3.00 0.47 62% 37% Resume [high priority] thread
0.78 0.00 2.00 0.35 76% 22% Thread switch
0.13 0.00 1.00 0.22 87% 87% Scheduler lock
0.34 0.00 1.00 0.45 66% 66% Scheduler unlock [0 threads]
0.30 0.00 1.00 0.42 70% 70% Scheduler unlock [1 suspended]
0.26 0.00 1.00 0.38 74% 74% Scheduler unlock [many suspended]
0.29 0.00 1.00 0.41 71% 71% Scheduler unlock [many low prio]
0.22 0.00 1.00 0.34 78% 78% Init mutex
0.50 0.00 1.00 0.50 100% 50% Lock [unlocked] mutex
0.47 0.00 1.00 0.50 53% 53% Unlock [locked] mutex
0.47 0.00 1.00 0.50 53% 53% Trylock [unlocked] mutex
0.44 0.00 1.00 0.49 56% 56% Trylock [locked] mutex
0.25 0.00 1.00 0.38 75% 75% Destroy mutex
4.00 4.00 4.00 0.00 100% 100% Unlock/Lock mutex
0.22 0.00 1.00 0.34 78% 78% Create mbox
0.13 0.00 1.00 0.22 87% 87% Peek [empty] mbox
0.50 0.00 1.00 0.50 100% 50% Put [first] mbox
0.09 0.00 1.00 0.17 90% 90% Peek [1 msg] mbox
0.47 0.00 1.00 0.50 53% 53% Put [second] mbox
0.16 0.00 1.00 0.26 84% 84% Peek [2 msgs] mbox
0.56 0.00 1.00 0.49 56% 43% Get [first] mbox
0.56 0.00 1.00 0.49 56% 43% Get [second] mbox
0.50 0.00 1.00 0.50 100% 50% Tryput [first] mbox
0.44 0.00 1.00 0.49 56% 56% Peek item [non-empty] mbox
0.47 0.00 1.00 0.50 53% 53% Tryget [non-empty] mbox
0.44 0.00 1.00 0.49 56% 56% Peek item [empty] mbox
0.41 0.00 1.00 0.48 59% 59% Tryget [empty] mbox
0.13 0.00 1.00 0.22 87% 87% Waiting to get mbox
0.13 0.00 1.00 0.22 87% 87% Waiting to put mbox
0.25 0.00 1.00 0.38 75% 75% Delete mbox
2.59 2.00 3.00 0.48 59% 40% Put/Get mbox
0.16 0.00 1.00 0.26 84% 84% Init semaphore
0.34 0.00 1.00 0.45 65% 65% Post [0] semaphore
0.44 0.00 1.00 0.49 56% 56% Wait [1] semaphore
0.31 0.00 1.00 0.43 68% 68% Trywait [0] semaphore
0.41 0.00 1.00 0.48 59% 59% Trywait [1] semaphore
0.16 0.00 1.00 0.26 84% 84% Peek semaphore
0.19 0.00 1.00 0.30 81% 81% Destroy semaphore
2.31 2.00 3.00 0.43 68% 68% Post/Wait semaphore
0.25 0.00 1.00 0.38 75% 75% Create counter
0.19 0.00 1.00 0.30 81% 81% Get counter value
0.16 0.00 1.00 0.26 84% 84% Set counter value
0.59 0.00 1.00 0.48 59% 40% Tick counter
0.13 0.00 1.00 0.22 87% 87% Delete counter
0.13 0.00 1.00 0.22 87% 87% Init flag
0.50 0.00 1.00 0.50 100% 50% Destroy flag
0.34 0.00 1.00 0.45 65% 65% Mask bits in flag
0.50 0.00 1.00 0.50 100% 50% Set bits in flag [no waiters]
0.66 0.00 1.00 0.45 65% 34% Wait for flag [AND]
0.59 0.00 1.00 0.48 59% 40% Wait for flag [OR]
0.72 0.00 1.00 0.40 71% 28% Wait for flag [AND/CLR]
0.66 0.00 1.00 0.45 65% 34% Wait for flag [OR/CLR]
0.13 0.00 1.00 0.22 87% 87% Peek on flag
0.25 0.00 1.00 0.38 75% 75% Create alarm
0.69 0.00 1.00 0.43 68% 31% Initialize alarm
0.38 0.00 1.00 0.47 62% 62% Disable alarm
0.69 0.00 1.00 0.43 68% 31% Enable alarm
0.50 0.00 1.00 0.50 100% 50% Delete alarm
0.53 0.00 1.00 0.50 53% 46% Tick counter [1 alarm]
2.19 2.00 3.00 0.30 81% 81% Tick counter [many alarms]
1.00 1.00 1.00 0.00 100% 100% Tick & fire counter [1 alarm]
13.06 13.00 14.00 0.12 93% 93% Tick & fire counters [>1 together]
2.56 2.00 3.00 0.49 56% 43% Tick & fire counters [>1 separately]
3.00 3.00 3.00 0.00 100% 100% Alarm latency [0 threads]
2.05 2.00 3.00 0.10 94% 94% Alarm latency [2 threads]
2.62 2.00 3.00 0.47 61% 38% Alarm latency [many threads]
4.01 4.00 5.00 0.01 99% 99% Alarm -> thread resume latency
0.00 0.00 0.00 0.00 Clock/interrupt latency
1.83 1.00 2.00 0.00 Clock DSR latency
200 180 212 Worker thread stack used (stack size 1088)
All done, main thrd : stack used 804 size 1536
All done : Idlethread stack used 172 size 1280
Timing complete - 29740 ms total
PASS:<Basic timing OK>
EXIT:<done>| |  | |
| Hardware debugging support |  | Test Programs |
| 2024-12-10 | eCosPro Non-Commercial Public License |