Configuration

Configuration
	Chapter 307. STM32H7 Nucleo-144 Platform HAL

Overview

The STM32H7 Nucleo-144 board platform HAL package CYGPKG_HAL_CORTEXM_STM32_NUCLEO144 is loaded automatically when eCos is configured for the nucleo144_stm32h723 target. It should never be necessary to load this package explicitly. Unloading the package should only happen as a side effect of switching target hardware.

Startup

The STM32H7 Nucleo-144 board platform HAL package supports two startup types:

ROM

This startup type can be used for finished applications which will be programmed into internal flash at location 0x08000000. Data and BSS will be put into internal SRAM starting from 0x240003CC. Internal SRAM below this address is reserved for vector tables. The application will be self-contained with no dependencies on services provided by other software. The program expects to boot from reset with ROM mapped at location zero. It will then transfer control to the 0x08000000 region. eCos startup code will perform all necessary hardware initialization.

This startup type will normally be used for production applications. It may also be used for development but over-use of flash during debugging may result in flash wear. It is advised to use the JTAG startup type during development if possible.

JTAG

This is the startup type used to build applications that are loaded via the hardware debugger interface. The application will be self-contained with no dependencies on services provided by other software. The program expects to be loaded into on-chip SRAM from 0x24000000 and entered at that address. eCos startup code will perform all necessary hardware initialization, though since the application is loaded via the hardware debugger interface the host debug environment may perform some initialization.

This is the startup type normally used during application development, since it avoids wear on the flash memory. However, SRAM is only 320kiB and not all applications will fit solely into SRAM. In such cases, a ROM startup application should be used.

SPI Driver

An SPI bus driver is available for the STM32 in the package “ST STM32 SPI driver” (CYGPKG_DEVS_SPI_CORTEXM_STM32).

SPI bus 1 is instantiated at CYGPKG_HAL_CORTEXM_STM32_NUCLEO144_SPI and is available on Arduino header CN7. No SPI devices are instantiated for this platform by default.

Consult the generic SPI driver API documentation in the eCosPro Reference Manual for further details on SPI support in eCosPro, along with the configuration options in the STM32 SPI device driver.

I²C Driver

The STM32 variant HAL provides the main I²C hardware driver itself, configured at CYGPKG_HAL_STM32_I2C. However, the platform I²C support can also be configured separately at CYGPKG_HAL_CORTEXM_STM32_NUCLEO144_I2C. This enables I²C bus 4 which is available on Arduino header CN7.

Flash Driver

The STM32's on-chip Flash may be programmed and managed using the Flash driver located in the “STM32 Flash memory support” (CYGPKG_DEVS_FLASH_STM32) package. This driver is enabled automatically if the generic “Flash device drivers” (CYGPKG_IO_FLASH) package is included in the eCos configuration. The driver will configure itself automatically for the size and parameters of the specific STM32 variant present on the STM32H7 Nucleo-144 board.

A number of aspects of Flash driver behaviour can be configured within that driver, such as program/erase parallelism and program burst size. Consult the driver for more details.

OCTOSPI Flash Driver

When OCTOSPI NOR flash support is enabled in the configuration with CYGHWR_HAL_CORTEXM_STM32_FLASH_OCTOSPI, then the cyg_stm32_octospi1_device device is exported and can be accessed via the standard flash API. The device is given a logical base address to match its physical base address of 0x90000000 (corresponding to FMC bank 4) when it is memory mapped (if CYGFUN_DEVS_FLASH_OCTOSPI1_CORTEXM_STM32_MEMMAPPED is enabled in the OCTOSPI driver, which is not the default). When memory mapping is disabled, using the eCos Flash API will still allow the device to be read/written at that logical base address.

Ethernet Driver

The Ethernet MAC is connected to a LAN8742A PHY via the RMII interface and thence to a RJ45 connector at CN143. The external 25MHz crystal X4 is used to supply the clock.

Note

	Note
It is highly recommended that the configuration option `CYGHWR_HAL_CORTEXM_STM32_SRAM_ALTERNATE` is ENABLED. Enabling that feature configures the Ethernet driver RX memory buffers to the SRAM2 space in the D2 domain. This is required to avoid an undocumented STM32H723 revZ errata where the Ethernet MAC would occasionally (rare) corrupt memory if the AXI SRAM was used for the RX buffers. The downside of the option is that it will mean a smaller number of RX buffers being available than is possible with the larger (main) AXI SRAM space.

It is highly recommended that the configuration option CYGHWR_HAL_CORTEXM_STM32_SRAM_ALTERNATE is ENABLED. Enabling that feature configures the Ethernet driver RX memory buffers to the SRAM2 space in the D2 domain. This is required to avoid an undocumented STM32H723 revZ errata where the Ethernet MAC would occasionally (rare) corrupt memory if the AXI SRAM was used for the RX buffers. The downside of the option is that it will mean a smaller number of RX buffers being available than is possible with the larger (main) AXI SRAM space.

ADC Driver

The STM32 processor variant HAL provides an ADC driver. The STM32H7 Nucleo-144 platform HAL enables the support for all three devices and for configuration of the respective ADC device input channels.

Consult the generic ADC driver API documentation in the eCosPro Reference Manual for further details on ADC support in eCosPro, along with the configuration options in the STM32 ADC device driver.


Setup		Hardware debugging support

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