| The HAL Port | ||
|---|---|---|
 | Chapter 323. NXP MIMXRT1xxx-EVK Platform HAL |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the IMXRT1050-EVKB and MIMXRT1064-EVK board hardware, and should be read in conjunction with that specification. The MIMXRT1xxx-EVK platform HAL package complements the Cortex-M architectural HAL and the i.MX variant HAL. It provides functionality which is specific to the target boards.
Startup
For the SRAM, JTAG,
JSDRAM, RBRAM and
RBSRAM startups, the HAL will perform
initialization, programming the various internal registers
including the PLL, peripheral clocks and pin multiplexing.
The details of the early hardware startup may be found in
the src/imx_misc.c in both
hal_system_init() and
hal_platform_init().
![[Note]](pix/note.png) | Note |
|---|---|
Some of the initial I/O run-time configuration is performed by the iMX boot ROM parsing the IVT+DCD binary structures that describe a bootable image. The relevant i.MX RTxxx PRM (Processor Reference Manual) documentation should be consulted for a detailed overview if required. |
Memory Map
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory areas are as follows:
- Internal SRAM
-
This is located at address 0x20200000 of the memory
space, and is 512KiB in size for RT105x CPUs and 1MiB
in size for the RT1064. The eCos VSR table occupies
the bottom 704 bytes, with the virtual vector table
starting at 0x200002C0 and extending to 0x200003C0.
Depending on the startup type the top of SRAM may have
CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZEbytes reserved for the interrupt stack, as well as an uncached area for driver/DMA use. The remainder of internal SRAM is available for use by applications. - External SDRAM
This is located at address 0x800000000 of the memory space. This region is 32MiB in size. Standalone
JSDRAMor RedBoot loadedRAMapplications are by default configured to run from this memory. This memory is only available after either A) an application has been loaded from a boot device, since it is initialized by the DCD that is part of the boot image or B) configured by the H/W debugger connection script.For example, if RedBoot is installed as the bootable application then the DCD prefixed to the RedBoot application configures the SDRAM as needed.
- On-Chip Peripherals
- These are accessible at locations 0x40000000 and 0xE0000000 upwards. Descriptions of the contents can be found in the i.MX RT10XX User Manual.
- Flash
For the RT1052 and RT1064 the external (off-chip) QSPI flash is mapped from address 0x60000000. For the RT1052 this external flash is the bootable flash device.
For the RT1064 the “external” (SiP) QSPI attached to FlexSPI2 is mapped from address 0x70000000. For the RT1064 this SiP flash is the bootable flash device.
Linker Scripts
The platform linker script defines the following symbols:
- hal_vsr_table
- This defines the location of the VSR table. This is set to 0x20200000 for all startup types, and space for 176 entries is reserved.
- hal_virtual_vector_table
- This defines the location of the virtual vector table used to communicate between a ROM monitor and an eCos application. If required this is allocated right after the VSR table, at 0x202002C0.
- hal_interrupt_stack
- This defines the location of the interrupt stack. This is allocated to the top of application available SRAM or SDRAM depending on the startup type.
- hal_startup_stack
- This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.
Real-time characterization
The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built for JTAG startup on a MIMXRT1050-EVK board.
Example 323.1. MIMXRT1050-EVK Real-time characterization
Configured
Testing parameters:
Clock samples: 32
Threads: 25
Thread switches: 128
Mutexes: 1165
Mailboxes: 340
Semaphores: 2040
Scheduler operations: 128
Counters: 680
Flags: 1360
Alarms: 582
Stack Size: 1088
Startup, main thrd : stack used 356 size 2048
Startup : Idlethread stack used 76 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 7.84 microseconds (7 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 25
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1088
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
INFO:<Ctrl-C disabled until test completion>
6.64 5.00 8.00 0.72 76% 8% Create thread
1.44 1.00 2.00 0.49 56% 56% Yield thread [all suspended]
1.56 1.00 2.00 0.49 56% 44% Suspend [suspended] thread
1.36 1.00 2.00 0.46 64% 64% Resume thread
2.04 2.00 3.00 0.08 96% 96% Set priority
0.32 0.00 1.00 0.44 68% 68% Get priority
3.20 3.00 5.00 0.34 84% 84% Kill [suspended] thread
1.48 1.00 2.00 0.50 52% 52% Yield [no other] thread
1.96 1.00 3.00 0.15 88% 8% Resume [suspended low prio] thread
1.40 1.00 2.00 0.48 60% 60% Resume [runnable low prio] thread
2.04 2.00 3.00 0.08 96% 96% Suspend [runnable] thread
1.52 1.00 2.00 0.50 52% 48% Yield [only low prio] thread
1.40 1.00 2.00 0.48 60% 60% Suspend [runnable->not runnable]
3.16 3.00 5.00 0.28 88% 88% Kill [runnable] thread
3.52 3.00 5.00 0.54 96% 52% Destroy [dead] thread
7.52 7.00 8.00 0.50 52% 48% Destroy [runnable] thread
6.80 6.00 9.00 0.51 60% 32% Resume [high priority] thread
2.34 2.00 4.00 0.46 66% 66% Thread switch
0.33 0.00 1.00 0.44 67% 67% Scheduler lock
1.21 1.00 2.00 0.33 78% 78% Scheduler unlock [0 threads]
1.26 1.00 2.00 0.38 74% 74% Scheduler unlock [1 suspended]
1.24 1.00 2.00 0.37 75% 75% Scheduler unlock [many suspended]
1.26 1.00 2.00 0.38 74% 74% Scheduler unlock [many low prio]
0.50 0.00 1.00 0.50 100% 50% Init mutex
1.81 1.00 3.00 0.36 75% 21% Lock [unlocked] mutex
1.88 1.00 2.00 0.22 87% 12% Unlock [locked] mutex
1.59 1.00 2.00 0.48 59% 40% Trylock [unlocked] mutex
1.53 1.00 2.00 0.50 53% 46% Trylock [locked] mutex
0.44 0.00 1.00 0.49 56% 56% Destroy mutex
10.00 10.00 10.00 0.00 100% 100% Unlock/Lock mutex
0.56 0.00 1.00 0.49 56% 43% Create mbox
0.38 0.00 1.00 0.47 62% 62% Peek [empty] mbox
1.81 1.00 2.00 0.31 81% 18% Put [first] mbox
0.38 0.00 1.00 0.47 62% 62% Peek [1 msg] mbox
1.69 1.00 3.00 0.47 62% 34% Put [second] mbox
0.38 0.00 1.00 0.47 62% 62% Peek [2 msgs] mbox
1.78 1.00 3.00 0.39 71% 25% Get [first] mbox
1.72 1.00 2.00 0.40 71% 28% Get [second] mbox
1.59 1.00 2.00 0.48 59% 40% Tryput [first] mbox
1.53 1.00 2.00 0.50 53% 46% Peek item [non-empty] mbox
1.56 1.00 2.00 0.49 56% 43% Tryget [non-empty] mbox
1.38 1.00 2.00 0.47 62% 62% Peek item [empty] mbox
1.50 1.00 2.00 0.50 100% 50% Tryget [empty] mbox
0.47 0.00 1.00 0.50 53% 53% Waiting to get mbox
0.50 0.00 1.00 0.50 100% 50% Waiting to put mbox
0.53 0.00 1.00 0.50 53% 46% Delete mbox
6.66 6.00 7.00 0.45 65% 34% Put/Get mbox
0.50 0.00 1.00 0.50 100% 50% Init semaphore
1.44 1.00 2.00 0.49 56% 56% Post [0] semaphore
1.59 1.00 2.00 0.48 59% 40% Wait [1] semaphore
1.34 1.00 2.00 0.45 65% 65% Trywait [0] semaphore
1.38 1.00 2.00 0.47 62% 62% Trywait [1] semaphore
0.44 0.00 1.00 0.49 56% 56% Peek semaphore
0.44 0.00 1.00 0.49 56% 56% Destroy semaphore
6.31 6.00 7.00 0.43 68% 68% Post/Wait semaphore
0.75 0.00 1.00 0.38 75% 25% Create counter
0.47 0.00 1.00 0.50 53% 53% Get counter value
0.38 0.00 1.00 0.47 62% 62% Set counter value
1.81 1.00 2.00 0.31 81% 18% Tick counter
0.50 0.00 1.00 0.50 100% 50% Delete counter
0.41 0.00 1.00 0.48 59% 59% Init flag
1.47 1.00 3.00 0.53 56% 56% Destroy flag
1.25 1.00 2.00 0.38 75% 75% Mask bits in flag
1.53 1.00 2.00 0.50 53% 46% Set bits in flag [no waiters]
1.91 1.00 3.00 0.23 84% 12% Wait for flag [AND]
1.97 1.00 3.00 0.12 90% 6% Wait for flag [OR]
1.91 1.00 3.00 0.23 84% 12% Wait for flag [AND/CLR]
1.94 1.00 2.00 0.12 93% 6% Wait for flag [OR/CLR]
0.34 0.00 1.00 0.45 65% 65% Peek on flag
0.88 0.00 1.00 0.22 87% 12% Create alarm
2.47 2.00 3.00 0.50 53% 53% Initialize alarm
1.47 1.00 2.00 0.50 53% 53% Disable alarm
2.38 2.00 3.00 0.47 62% 62% Enable alarm
1.59 1.00 2.00 0.48 59% 40% Delete alarm
1.84 1.00 2.00 0.26 84% 15% Tick counter [1 alarm]
7.34 7.00 8.00 0.45 65% 65% Tick counter [many alarms]
2.97 2.00 3.00 0.06 96% 3% Tick & fire counter [1 alarm]
42.19 42.00 43.00 0.30 81% 81% Tick & fire counters [>1 together]
8.47 8.00 9.00 0.50 53% 53% Tick & fire counters [>1 separately]
7.00 7.00 7.00 0.00 100% 100% Alarm latency [0 threads]
6.59 6.00 7.00 0.49 58% 41% Alarm latency [2 threads]
6.67 6.00 7.00 0.44 67% 32% Alarm latency [many threads]
11.02 11.00 13.00 0.03 99% 99% Alarm -> thread resume latency
0.00 0.00 0.00 0.00 Clock/interrupt latency
3.08 2.00 4.00 0.00 Clock DSR latency
180 148 228 Worker thread stack used (stack size 1088)
All done, main thrd : stack used 704 size 2048
All done : Idlethread stack used 172 size 1280
Timing complete - 29820 ms total
PASS:<Basic timing OK>
EXIT:<done>
Platform specific tests
A single platform specific test is available.
platform
The platform test is a simple
validity check application. It tests application access to
some basic functionality, as well as providing some
diagnostic information on system settings.
The test source is set up for automated testing (e.g. as
used in the eCosCentric test farm ). However, the
__MANUAL manifest can be manually
enabled to provide some extra testing requiring user
interaction. Currently __MANUAL
controls access to a simple polled and interrupt-driven
GPIO SW8 (USER_BUTTON) test. That
specific test case implements an example of using the
de-multiplexed GPIO interrupt support.
| |  | |
| Configuration |  | Part LXXXI. H8300 Architecture |
| 2025-10-02 | Open Publication License |