On-chip Subsystems and Peripherals — Hardware Support
The LPC1XXX parts include on-chip SRAM, and on-chip FLASH. The RAM consists of up to 64KiB in one or two disjoint blocks, and the FLASH can be up to 512KiB in size depending on model.
Typically, an eCos platform HAL port will expect a GDB stub ROM monitor to be programmed into the LPC1XXX on-chip ROM memory for development, and the board would boot this image from reset. The stub ROM provides GDB stub functionality so it is then possible to download and debug stand-alone and eCos applications via the gdb debugger using serial interfaces or other debug channels. The JTAG interface may also be used for development if a suitable JTAG device is available. For production purposes, applications are programmed into on-chip FLASH and will be self-booting.
a driver for the on-chip flash. This driver conforms to the
Version 2 flash driver API. It queries the microcontroller's
device capabilities registers to determine the size and layout of
the flash at runtime. This driver is shared with the LPC2xxx
microcontroller family, and its name reflects that.
The LPC1XXX does not contain any caches, however, the variant HAL
cyg/hal/hal_cache.h header to
satisfy generic code. This header describes zero sized caches and
provides null macros for the required functions.
The LPC1XXX variant HAL supports basic polled HAL diagnostic I/O
over any of the on-chip serial devices. There is also a fully
interrupt-driven serial device driver suitable for eCos
applications for all on-chip serial devices. The serial driver
consists of an eCos package:
CYGPKG_IO_SERIAL_CORTEXM_LPC1XXX which provides
configuration for the
package. Using the HAL diagnostic I/O support, any of these
devices can be used by the ROM monitor for
communication with GDB. If a device is needed by the application,
either directly or via the serial driver, then it cannot also be
used for GDB communication using the HAL I/O support. An
alternative serial port should be used instead.
The HAL defines CDL interfaces,
CYGINT_HAL_LPC1XXX_UART3 for each of the
possible UARTs. The platform HAL CDL should contain an
implements directive for each such UART that
is available for use on the board. This will enable use of the
UART for diagnostic use.
UARTs 0, 2 and 3 only support TX and RX lines, however UART1 supports the full set of modem control lines.
The LPC1XXX HAL relies on the architectural HAL to provide support
for the interrupts directly routed to the NVIC. The
cyg/hal/var_intr.h header defines
the vector mapping for these.
The variant HAL provides support for packaging the configuration of a GPIO line into a single 32-bit descriptor that can then be used with macros to configure the pin and set and read its value.
The variant HAL provides support for packaging the clock control parameters of a device into a single 32-bit descriptor that can then be used with macros to enable and disable the device's clock.
A separate driver,
provides support for I²C devices. The platform HAL must define
the set of devices attached to each bus and must also configure
the pins used for each I²C bus.
The SSP device is based on the ARM PL022 SSP primecell and SPI
support is provided via the
CYGPKG_DEVS_SPI_ARM_PL022 driver. The
platform HAL must define the bus instances and devices attached
The LPC1XXX HAL contains support for gprof-base
profiling using a sampling timer. The default timer used is Timer
0. The timer used is selected by a set
src/lpc1xxx_misc.c which can be changed to
refer to a different timer if required. This timer is only
CYGPKG_PROFILE_GPROF is enabled,
otherwise it remains available for application use.
The platform HAL must provide the input clock frequency
CYGHWR_HAL_LPC1XXX_INPUT_CLOCK) in its
CDL file. This is then combined with the following options defined
in this package to define the default system clocks:
This defines the source of
the main system clock. It can take one of three values:
IRCselects the internal ocillator,
OSCselects the main ocillator,
RTCselects the 32KHz internal clock. It defaults to
- This defines the divider applied to the 400MHz PLL output to generate the system clock. This can take values between 1 and 16. The default value is 4, giving a 50MHz system clock.
- This defines the multiplier applied by PLL0 to the selected clock input. It can vary between 6 and 512. The default is 6.
- This defines the pre-divider for PLL0. It may take any value betwen 1 and 32. The default is 1.
This defines the source of the main CPU clock, CCLK. The
PLLto select PLL0 and
SYSCLKto bypass the PLL and use the system clock directly. The default is
- This defines the divider applied to the selected CCLK. It may range between 3 and 256. The default is 3.
The actual frequency of the system clock, in Hz, is stored in the
the frequency of the PLL output clock is stored
hal_lpc1xxx_pllclk and of CCLK
hal_lpc1xxx_cclk. The clock supplied to the
SysTick timer, CCLK, is also assigned to
hal_cortexm_systick_clock. These variables are
used, rather than configuration options, in anticipation of future
support for power management by varying the system clock rate.
|2021-04-29||eCosPro Non-Commercial Public License|