| The HAL Port | ||
|---|---|---|
 | Chapter 269. Logic Zoom Board Support |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the Zoom L138 hardware, and should be read in conjunction with that specification. The platform HAL package complements the ARM architectural HAL, the ARM9 variant HAL and the OMAP L1xx processor HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROM startup, the HAL will perform additional
initialization. This is all done in the
PLATFORM_SETUP1 macro in the assembler header
file hal_platform_setup.h.
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- SDRAM
- This is located at address 0xC0000000 of the physical memory space. The HAL configures the MMU to retain the SDRAM at virtual address 0xC0000000, but in order to assign hardware exception vectors vectors at address 0x00000000, the HAL also uses the MMU to create a clone of this memory at virtual address 0x00000000. The same memory is also accessible uncached and unbuffered at virtual location 0xD0000000 for use by devices. The first 32 bytes are used for hardware exception vectors. The next 32 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x4000 to 0x8000. For ROM startup, all remaining SDRAM is available. For RAM startup, available RAM starts at virtual location 0xC0040000, with the bottom 256kB reserved for use by RedBoot. ROM applications are loaded starting at 0xC0008000, which leaves space for the User Boot Loader.
- On-chip SRAM
- There are a number of on-chip SRAM areas. These are identity mapped unbuffered and uncached with their physical addresses.
- SPI NOR Flash
- SPI NOR flash media can only be accessed with the Flash API. For the purposes of this API a placeholder address range has been allocated as if the Flash is present at this address. The base of this address range is 0x70000000. This reserved range is not real memory and any attempt to access it directly by the processor other than via the Flash API will result in a memory address exception.
- On-chip Peripheral Registers
- These are located at various addresses in the physical memory space. When the MMU is enabled, it sets up a direct, uncached, unbuffered mapping so that these registers remain accessible at their physical locations.
- Off-chip Peripherals
- eCos uses the SDRAM, ethernet PHY, MMC/SD, and SPI flash facilities on the Zoom L138 board. eCos does not currently make any use of any other off-chip peripherals present on this board.
SPI NOR Flash
eCos supports SPI access to the NOR flash on the board. The device is typically used to contain RedBoot and flash configuration data.
Accesses to SPI flash are performed via the Flash API, using 0x70000000 or as the nominal address of the device, although it does not truly exist in the processor address space.
Since SPI flash is not directly addressable, access from RedBoot is only possible using fis command operations.
Real-time characterization
The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built in ARM mode, which provides better performance than Thumb mode.
Example 269.1. zoom_l138 Real-time characterization
Startup, main stack : stack used 392 size 3920
Startup : Interrupt stack used 504 size 4096
Startup : Idlethread stack used 88 size 2048
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 4.52 microseconds (9 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 64
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
3.21 2.00 8.50 0.53 60% 25% Create thread
0.80 0.50 2.50 0.27 54% 43% Yield thread [all suspended]
1.08 0.50 3.00 0.15 85% 1% Suspend [suspended] thread
1.07 0.50 2.50 0.18 76% 6% Resume thread
1.51 1.00 5.00 0.19 73% 17% Set priority
0.90 0.50 1.50 0.22 64% 28% Get priority
2.42 2.00 10.50 0.36 54% 42% Kill [suspended] thread
0.79 0.50 2.00 0.26 53% 45% Yield [no other] thread
1.45 1.00 4.00 0.22 67% 25% Resume [suspended low prio] thread
1.05 0.50 2.50 0.14 81% 6% Resume [runnable low prio] thread
1.50 1.00 4.00 0.17 71% 17% Suspend [runnable] thread
0.80 0.50 2.50 0.27 53% 45% Yield [only low prio] thread
1.08 0.50 2.50 0.16 81% 3% Suspend [runnable->not runnable]
2.14 1.50 7.50 0.28 78% 4% Kill [runnable] thread
2.33 2.00 6.00 0.31 50% 46% Destroy [dead] thread
2.96 2.50 7.00 0.26 62% 28% Destroy [runnable] thread
4.34 3.50 9.50 0.43 82% 6% Resume [high priority] thread
1.48 1.00 4.00 0.08 90% 7% Thread switch
0.43 0.00 1.00 0.13 84% 14% Scheduler lock
0.70 0.50 1.00 0.24 60% 60% Scheduler unlock [0 threads]
0.69 0.50 1.00 0.24 61% 61% Scheduler unlock [1 suspended]
0.70 0.50 1.50 0.24 60% 60% Scheduler unlock [many suspended]
0.70 0.50 1.00 0.24 60% 60% Scheduler unlock [many low prio]
0.45 0.00 2.00 0.17 78% 18% Init mutex
1.02 0.50 2.50 0.12 84% 9% Lock [unlocked] mutex
1.13 0.50 3.50 0.29 68% 9% Unlock [locked] mutex
0.98 0.50 2.50 0.12 84% 12% Trylock [unlocked] mutex
0.88 0.50 1.50 0.21 68% 28% Trylock [locked] mutex
0.50 0.00 1.50 0.06 90% 6% Destroy mutex
3.14 3.00 6.50 0.25 90% 90% Unlock/Lock mutex
0.52 0.50 1.00 0.03 96% 96% Create mbox
0.53 0.50 1.00 0.06 93% 93% Peek [empty] mbox
1.17 1.00 3.00 0.26 75% 75% Put [first] mbox
0.73 0.50 1.00 0.25 53% 53% Peek [1 msg] mbox
1.17 1.00 3.00 0.26 75% 75% Put [second] mbox
0.55 0.50 1.00 0.08 90% 90% Peek [2 msgs] mbox
1.20 1.00 3.00 0.28 68% 68% Get [first] mbox
1.30 1.00 2.00 0.26 53% 43% Get [second] mbox
1.09 1.00 2.50 0.16 87% 87% Tryput [first] mbox
1.11 1.00 2.50 0.18 84% 84% Peek item [non-empty] mbox
1.16 1.00 2.50 0.23 75% 75% Tryget [non-empty] mbox
1.06 0.50 2.50 0.14 87% 3% Peek item [empty] mbox
0.98 0.50 2.50 0.12 84% 12% Tryget [empty] mbox
0.75 0.50 1.00 0.25 100% 50% Waiting to get mbox
0.55 0.50 1.00 0.08 90% 90% Waiting to put mbox
0.81 0.50 2.50 0.31 93% 50% Delete mbox
2.42 2.00 7.00 0.42 93% 50% Put/Get mbox
0.44 0.00 0.50 0.11 87% 12% Init semaphore
0.88 0.50 2.00 0.26 59% 34% Post [0] semaphore
0.88 0.50 2.00 0.23 65% 31% Wait [1] semaphore
0.84 0.50 2.00 0.26 59% 37% Trywait [0] semaphore
0.77 0.50 1.00 0.25 53% 46% Trywait [1] semaphore
0.55 0.00 1.50 0.17 75% 9% Peek semaphore
0.53 0.00 1.50 0.12 84% 6% Destroy semaphore
2.13 2.00 5.00 0.23 90% 90% Post/Wait semaphore
0.55 0.50 2.00 0.09 96% 96% Create counter
0.67 0.00 1.50 0.26 62% 3% Get counter value
0.50 0.00 1.00 0.06 87% 6% Set counter value
1.03 0.50 2.00 0.12 84% 6% Tick counter
0.64 0.00 1.50 0.23 68% 3% Delete counter
0.42 0.00 0.50 0.13 84% 15% Init flag
0.91 0.50 2.50 0.23 68% 28% Destroy flag
0.81 0.50 2.00 0.27 53% 43% Mask bits in flag
0.91 0.50 2.00 0.20 71% 25% Set bits in flag [no waiters]
1.08 1.00 3.50 0.15 96% 96% Wait for flag [AND]
0.98 0.50 2.00 0.09 87% 9% Wait for flag [OR]
1.03 1.00 2.00 0.06 96% 96% Wait for flag [AND/CLR]
0.98 0.50 2.00 0.09 87% 9% Wait for flag [OR/CLR]
0.41 0.00 0.50 0.15 81% 18% Peek on flag
0.58 0.50 3.00 0.15 96% 96% Create alarm
1.67 1.00 5.50 0.36 87% 9% Initialize alarm
1.00 0.50 2.00 0.06 90% 6% Disable alarm
1.55 1.00 4.50 0.30 62% 21% Enable alarm
1.06 1.00 2.50 0.12 93% 93% Delete alarm
0.94 0.50 1.50 0.14 81% 15% Tick counter [1 alarm]
3.67 3.50 4.00 0.23 65% 65% Tick counter [many alarms]
1.39 1.00 2.50 0.22 68% 28% Tick & fire counter [1 alarm]
17.56 17.50 18.00 0.11 87% 87% Tick & fire counters [>1 together]
4.09 4.00 4.50 0.15 81% 81% Tick & fire counters [>1 separately]
4.01 4.00 5.00 0.02 99% 99% Alarm latency [0 threads]
4.47 4.00 5.50 0.21 63% 21% Alarm latency [2 threads]
8.21 6.50 10.00 0.64 47% 11% Alarm latency [many threads]
6.04 6.00 11.00 0.08 98% 98% Alarm -> thread resume latency
1.01 0.50 4.00 0.00 Clock/interrupt latency
1.85 1.00 5.50 0.00 Clock DSR latency
5 0 272 (main stack: 1328) Thread stack used (1360 total)
All done, main stack : stack used 1328 size 3920
All done : Interrupt stack used 140 size 4096
All done : Idlethread stack used 232 size 2048
Timing complete - 29920 ms total
PASS:<Basic timing OK>
EXIT:<done>Other Issues
The platform HAL does not affect the implementation of other parts of the eCos HAL specification. The OMAP L1xx processor HAL, ARM9 variant HAL, and the ARM architectural HAL documentation should be consulted for further details.
| |  | |
| JTAG debugging support |  | Chapter 270. Freescale i.MXxx Processor Support |
| 2024-12-10 | eCosPro Non-Commercial Public License |