eCos Support for the Versatile 926EJ-S Board — Overview


This document covers the ARM Versatile Platform Baseboard for the ARM926EJ-S development chip, hereafter referred to as the VPB926EJS. The VPB926EJS contains the ARM926EJ-S processor, 128Mb of SDRAM, 64MB of Intel Strataflash memory, 2Mb of static RAM, a SMSC LAN91C111 Ethernet MAC, and external connections for the three on-chip and one off-chip serial channels, ethernet and the various other peripherals supported by the ARM926EJ-S.

For typical eCos development, a RedBoot image is programmed into the flash memory, and the board will boot this image from reset. RedBoot provides gdb stub functionality so it is then possible to download and debug stand-alone and eCos applications via the gdb debugger. This can happen over either a serial line or over ethernet.

Supported Hardware

The flash memory consists of 256 blocks of 256k bytes each. In a typical setup, the first flash block is used for the ROMRAM RedBoot image. The topmost block is used to manage the flash and hold RedBoot fconfig values. The remaining 254 blocks between 0x34040000 and 0x37FBFFFF can be used by application code.

There is a serial driver CYGPKG_IO_SERIAL_ARM_PL011 which supports the ARM PL011 PrimeCell UARTs used by the VPB926EJS. The CYGPKG_IO_SERIAL_ARM_VPB926EJS package provides customization of this generic driver to the VPB926EJS hardware. These devices can be used by RedBoot for communication with the host. If any of these devices is needed by the application, either directly or via the serial driver, then it cannot also be used for RedBoot communication. Another communication channel such as ethernet should be used instead. The serial driver packages are loaded automatically when configuring for the VPB926EJS target.

There is an ethernet driver CYGPKG_DEVS_ETH_SMSC_LAN91CXX for the SMSC LAN91C111 ethernet device. A second package CYGPKG_DEVS_ETH_ARM_VPB926EJS is responsible for configuring this generic driver to the VPB926EJS hardware. These drivers are also loaded automatically when configuring for the VPB926EJS target.

eCos manages the on-chip interrupt controller. Timer 0 is used to implement the eCos system clock and the microsecond delay function. Other on-chip devices (Caches, UARTs, MPMC, SSMC, I²C etc.) are initialized only as far as is necessary for eCos to run. Other devices (PCI, SSP, SCI, GPIO etc.) are not touched.


The VPB926EJS port is intended to work with GNU tools configured for an arm-eabi target. The original port was undertaken using arm-elf-gcc version 3.2.1, arm-elf-gdb version 5.3, and binutils version 2.13.1.