HAL Port — Implementation Details
This section covers any remaining items of note related to the STR7xx variant support, not covered in previous sections.
If a platform port has support for the display of values on LEDs, that support is standardised to be accessible from C with the following function:
#include <cyg/infra/hal_diag.h> extern void hal_diag_led(int leds);
The platform HAL must provide the input clock frequency
CYGARC_HAL_STR7XX_INPUT_CLOCK) in its CDL file.
The STR7XX variant HAL port includes the header file
var_io.h which provides useful register
definitions used by eCos, that can also be freely used by applications.
It includes only limited register definitions for subsystems unused by
It may be found in the
include/cyg/hal directory relative to your
configuration's install tree, or alternatively in the source
However it should be properly included by applications by using the following
to allow for platform HALs to augment or override any relevant definitions:
The kernel idle thread is scheduled to run when the system has no
other tasks able to run. The idle thread can call a HAL supplied macro
to place the chip into an appropriate power saving mode instead of
just going around a busy loop. The STR7XX variant HAL defines the
HAL_IDLE_THREAD_ACTION macro to use the STR7XX
power control support to place the chip into
mode which will stop the processor clock, without disabling the
on-chip peripherals. This state continues until an interrupt is
Further power saving can be achieved by reducing the system clock
described above. This function only changes the clock frequencies; it
may also be necessary to change the values of dividers in various
peripherals to compensate. There are several routines supplied in the
HAL to do this.
hal_str7xx_uart_reinit() will cause all
the UART baud rate dividers to be reset to match the current value of
PCLK1. Note that there are limitations to the range of baud rates that
can be set, PCLK1 must be at least 16 times the required rate. Also,
the resolution of the baud rate divider may make certain baud rates
less accurate at different PCLK1 frequencies.
will cause the watchdog to be reinitialized with a timeout based on
the current value of PCLK2. The resolution of the prescaler and the
size of the 16 bit counter may render certain watchdog timeouts
unachievable at some clock rates.
will cause the main system timer to be reinitialized based on the
current value of PCLK2.
|2021-04-29||eCosPro Non-Commercial Public License|