HAL Port — Implementation Details
This documentation explains how the eCos HAL specification has been
mapped onto the STR710-EVAL Board hardware, and should be read in conjunction
with that specification. The STR710-EVAL Board platform HAL package complements
the ARM architectural HAL and the STR7XX variant HAL. It provides
functionality which is specific to the target board.
Following a hard or soft reset the HAL will initialize or reinitialize
many of the on-chip peripherals. There is an exception for RAM startup
applications which depend on a ROM monitor for certain services.
For ROM and JTAG startup, the HAL will perform additional
initialization, programming the various internal registers including
the PLL, peripheral clocks, GPIO pins and memory mapping control to
map internal RAM 0x0. The details of the early hardware startup may
be found in the header
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed
to generate the linker script. The key memory locations are as follows:
- External RAM
This is located at address 0x62000000 of the memory space, and is 4MiB
long. For ROM applications, all of RAM is available for use.
For RAM startup applications, RAM below 0x62020000 is
reserved for RedBoot and the remainder is available for the
- External ROM
This is located at address 0x60000000 of the memory space. If switches
SW13, SW14 and SW15 are all set to 2-3 this region will be mapped to 0x00000000 at
reset. This region is 4MiB in size. RedBoot is normally programmed
into this memory and the rest managed by the FIS flash file system.
- Internal RAM
This is located at address 0x20000000 of the memory space, and is 64KiB
in size. Normally this RAM area will be mapped to location 0x00000000
after bootstrap. The CPU vector table and the eCos VSR table occupy
the bottom 64 bytes. The virtual vector table starts at 0x00000050 and extends
to 0x00000150. The remainder of internal RAM is available for use by
- Internal ROM
This is located at address 0x40000000 of the memory space. If
switches SW13 and SW14 are set to 1-2 and SW15 to 2-3 this region
will be mapped to 0x00000000 at reset. This region is 256KiB
in size. Applications may be configured to run from this
memory by setting the
option. This memory is not managed by RedBoot's FIS system,
but it can be written using the fis write command
and erased using the fis erase command.
- on-chip peripherals
These are accessible at locations 0xC0000000 and 0xE0000000 upwards,
depending on which APB bus they are on. Descriptions of the
contents can be found in the STR7XX User Manual.