The HAL Port
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HAL Port — Implementation Details

Overview

This documentation explains how the eCos HAL specification has been mapped onto the hardware, and should be read in conjunction with that specification. The platform HAL package complements the ARM architectural HAL, the ARM9 variant HAL and the OMAP L1xx processor HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM startup, the HAL will perform additional initialization. This is all done in the PLATFORM_SETUP1 macro in the assembler header file hal_platform_setup.h.

Linker Scripts and Memory Maps

The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

SDRAM
This is located at address 0xC0000000 of the physical memory space. The HAL configures the MMU to retain the SDRAM at virtual address 0xC0000000, but in order to assign hardware exception vectors at address 0x00000000, the HAL also uses the MMU to create a clone of this memory at virtual address 0x00000000. The same memory is also accessible uncached and unbuffered at virtual location 0xD0000000 for use by devices. The first 32 bytes are used for hardware exception vectors. The next 32 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x4000 to 0x8000. For ROM startup, all remaining SDRAM is available. For RAM startup, available RAM starts at virtual location 0xC0040000, with the bottom 256kB reserved for use by RedBoot.
On-chip SRAM
There are a number of on-chip SRAM areas. These are identity mapped unbuffered and uncached with their physical addresses. eCos does not use any of these areas so they are all available to the application.
SPI NOR Flash
SPI NOR flash media can only be accessed with the Flash API. For the purposes of this API a placeholder address range has been allocated as if the Flash is present at this address. The base of this address range is 0x70000000. This reserved range is not real memory and any attempt to access it directly by the processor other than via the Flash API will result in a memory address exception.
On-chip Peripheral Registers
These are located at various addresses in the physical memory space. When the MMU is enabled, it sets up a direct, uncached, unbuffered mapping so that these registers remain accessible at their physical locations.
Off-chip Peripherals
eCos uses the SDRAM, ethernet PHY, SPI flash, and I²C EEPROM facilities on the board. eCos does not currently make any use of any other off-chip peripherals present on this board.

SPI NOR Flash

eCos supports SPI access to the NOR flash on the board. The device is typically used to contain RedBoot and flash configuration data.

Accesses to SPI flash are performed via the Flash API, using 0x70000000 or as the nominal address of the device, although it does not truly exist in the processor address space.

Since SPI flash is not directly addressable, access from RedBoot is only possible using fis command operations.

Other Issues

The platform HAL does not affect the implementation of other parts of the eCos HAL specification. The OMAP L1xx processor HAL, ARM9 variant HAL, and the ARM architectural HAL documentation should be consulted for further details.

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