HAL Port — Implementation Details
This documentation explains how the eCos HAL specification has been mapped onto the IXDP425 hardware, and should be read in conjunction with that specification. The IXDP425 platform HAL package complements the ARM architectural HAL, the XScale variant HAL and the IXP425 processor HAL. It provides functionality which is specific to the target board.
Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROM or ROMRAM startup, the HAL will perform additional
initialization, setting up the external RAM and programming the
various internal registers. This is all done in the
PLATFORM_SETUP1 macro in the assembler
Unless the Compact Flash IDE configuration option is selected, RedBoot uses the 4 digit LED display to indicate status during board initialization. Possible codes are:
Set the CPSR
Enable coprocessor access
Drain write and fill buffer
Setup expansion bus chip selects
Initialize SDRAM controller
Switch flash (CS0) from 0x00000000 to 0x50000000
Copy MMU table to RAM
Setup TTB and domain permissions
Enable branch target buffer
Drain write and fill buffer
Start up the eCos kernel or RedBoot
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- This is located at address 0x50000000 of the physical memory space. At initialization, the HAL uses the MMU to retain it at virtual address 0x50000000, while also providing an uncached mapping at 0xB0000000 and a data coherent mapping at 0xA0000000.
- This is located at address 0x00000000 of the physical memory space. The HAL uses the MMU to retain this at virtual address 0x00000000, along with an alias at 0x10000000. The same memory is also accessible uncached at virtual location 0x20000000 for use by devices, and at 0x30000000 for data coherent access. The first 32 bytes are used for hardware exception vectors. The next 32 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x4000 to 0x8000. For ROM/ROMRAM startup, all remaining SDRAM is available. For RAM startup, available RAM starts at virtual location 0x00080000, with the bottom 512 kilobytes reserved for use by RedBoot.
- On-chip Peripheral Registers
There are several regions in the memory map devoted to on-chip peripherals or on-chip device controllers. When the MMU is enabled, all these regions are set up with a direct, uncached and unbuffered mapping so that these registers remain accessible at their physical locations.
As such, the address space for the AHB Queue Manager (AQM) resides at 0x60000000; the PCI controller resides at 0xC0000000; the expansion bus controller configuration registers reside at 0xC4000000; the SDRAM controller configuration registers resides at 0xCC000000; and all remaining IXP425 on-chip peripherals reside in the block at 0xC8000000. This latter block includes peripheral control for on-chip high-speed and console UARTs, internal bus performance monitoring unit, interrupt controller, GPIO controller, timers, WAN/Voice and Ethernet NPEs, Ethernet MACs, and the USB controller.
- Off-chip Peripherals
RedBoot and eCos access the SDRAM, parallel NOR flash, and hex display on CS2 (mapped to 0x52000000). In addition a CompactFlash True IDE mode disk may be accessed via the expansion bus on CS1/CS2 (0x51000000/0x52000000), although the hex display is not usable in that case.
In addition a 64MiB PCI window is mapped to 0x48000000, for communication with devices on the PCI bus.
RedBoot and eCos do not currently make any use of any other off-chip peripherals present on the IXDP425 board.
Memory map summary
The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region.
X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid - not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Virtual Address Physical Address XCB Size (MB) Description 0x00000000 0x00000000 010 256 SDRAM (cached) 0x10000000 0x00000000 010 256 SDRAM (alias) 0x20000000 0x00000000 000 256 SDRAM (uncached) 0x30000000 0x00000000 010 256 SDRAM (cached, DC) 0x48000000 0x48000000 000 64 PCI Data 0x50000000 0x50000000 010 16 Flash (CS0, cached) 0x51000000 0x51000000 000 16 CF True IDE mode chip select #0 (CS1) 0x52000000 0x52000000 000 16 Hex display/CF True IDE mode chip select #1 (CS2) 0x53000000 0x53000000 000 80 CS3 - CS7 0x60000000 0x60000000 000 64 Queue Manager 0xA0000000 0x50000000 010 16 Flash (CS0, cached, DC) 0xB0000000 0x50000000 000 16 Flash (CS0, uncached) 0xC0000000 0xC0000000 000 1 PCI Controller 0xC4000000 0xC4000000 000 1 Exp. Bus Config 0xC8000000 0xC8000000 000 1 Misc IXP425 IO 0xCC000000 0xCC000000 000 1 SDRAM Config
The IXDP425 platform HAL does not affect the implementation of other parts of the eCos HAL specification. The XScale variant HAL, the IXP4xx processor HAL documentation and the ARM architectural HAL documentation should be consulted for further details.
|2023-04-25||Open Publication License|