HAL Port — Implementation Details
This documentation explains how the eCos HAL specification has been
mapped onto the LPC2468 OEM Board hardware, and should be read in
conjunction with that specification. The LPC2468
platform HAL package complements the ARM architectural HAL and the
LPC2xxx variant HAL. It provides functionality which is specific to
the target board.
Following a hard or soft reset the HAL will initialize or reinitialize
many of the on-chip peripherals.
There is an exception for RAM startup applications which
depend on a ROM monitor to do most of this.
For ROM startup, the HAL will perform additional initialization,
programming the various internal registers including PLL (for the
clocks); Memory Mapping control registers to map SRAM to 0x0; the
memory controller for access to external FLASH and SDRAM; and
the Memory Acceleration Module (MAM). The details of the early
hardware startup may be found in the header
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed
to generate the linker script. The key memory locations are as follows:
- on-chip Flash
This is located at address 0x0 of the memory space, although after
hardware initialization, the start of internal SRAM is mapped over
locations 0x0 to 0x40. This region ends at 0x80000. The MAM is
enabled to accelerate memory reads from this area. A driver is
available for using this flash via the eCos flash API.
- external Flash
This is located at address 0x80000000 of the memory space. It is not
used by default by eCos, although if RedBoot is asked to manage the
Flash, it reserves flash addresses 0x803F0000 thru 0x803FEFFF. If
RedBoot stores its configuration data in Flash, then addresses
0x803FF000 thru 0x803FFFFF are reserved by RedBoot.
- internal SRAM
This is located at address 0x40000000 of the memory space, ending at
location 0x4000FFFF. The first 64 bytes are mapped to location
- external SDRAM
This is located at address 0xa0000000 of the memory space, ending at
location 0xa2000000. For RAM startup, available SRAM starts at
location 0xa1100000, with the bottom 1Mbyte reserved for use by
- on-chip peripherals
These are accessible via location 0xE0000000 onwards. Descriptions
of the contents can be found in the LPC2468 User Manual.