Description

This document covers the configuration and usage of eCos and RedBoot on the Dream Chip Arria 10 SoM and baseboard Development kit. This board is fitted with avariant of the Arria 10 family of FPGAs and it therefore referred to in this document and the configuration system as the Dream Chip A10, to differentiate it from other Arria 10 development boards.

In addition to the Arria 10 FPGA, the board contains 2GiB SDRAM main memory, a 500Mib (64GiB) SPI NOR flash, a micro-SD card socket, a USB bridge connected to UART1, an Ethernet socket for an HPS Ethernet interface, plus a variety of connectors for other interfaces plus resources devoted to the FPGA. The extent of eCos support for the devices and peripherals on the board and the CPU is described below.

For typical eCos development, a RedBoot image is programmed into the SPI NOR flash memory, and the board will load this image from reset. RedBoot provides gdb stub functionality so it is then possible to download and debug stand-alone and eCos applications via the gdb debugger. This can happen over either a serial line or over Ethernet. Alternatively, RedBoot may be loaded from an SD card.

Support for SMP operation of the two Cortex-A9 CPUs on the SoC is available, although debugging support is restricted to use of an external JTAG debugger. There is no SMP support in RedBoot.

This documentation is expected to be read in conjunction with the Altera HPS processor HAL documentation and further device support and subsystems are described and documented there.

Supported Hardware

The SPI NOR flash consists of 1024 blocks of 64Ki bytes each. In a typical setup, the first 16Mib are reserved for the second-level bootstrap, in this case a port of U-Boot, plus the FPGA bitstreams. The 10 blocks from 1MiB are reserved for the ROM RedBoot image. The topmost block is used to manage the flash and also holds RedBoot fconfig values. The remaining blocks can be used by application code.

Serial support is through the CYGPKG_IO_SERIAL_GENERIC_16X5X generic driver package which is modified by the CYGPKG_IO_SERIAL_ARM_ALTERA_HPS driver package for the HPS. These packages can support all the serial devices on the HPS. However, this board only has UART1 connected to an external connector which this HAL indicates by implementing the CYGINT_HAL_ARM_CORTEXA_ALTERA_HPS_UART1 interface. This serial channel is used by RedBoot for communication with the host. If this device is needed by the application, either directly or via the serial driver, then it cannot also be used for RedBoot communication. Another communication channel such as Ethernet should be used instead. The serial driver package is loaded automatically when configuring for the dreamchip-a10 target.

There is an Ethernet driver CYGPKG_DEVS_ETH_DWC_GMAC for the on-chip Ethernet device. A separate package, CYGPKG_DEVS_ETH_DREAMCHIP_A10 configures this generic driver to the hardware. This driver is also loaded automatically when configuring for the dreamchip-a10 board.

There is a watchdog driver CYGPKG_DEVICES_WATCHDOG_DWWDT. This driver is also loaded automatically when configuring for the board.

The HPS processor HAL contains a driver for the MultiMedia Card Interface (MMC/SD). This driver is loaded automatically when configuring CYGPKG_DEVS_DISK_MMCSD_BUS for this target and allows use of MultiMediaCard (MMC) and Secure Digital (SD) flash storage cards within eCos, exported as block devices. Further documentation on the driver may be found in the Altera Hard Processor System Support HAL documentation.

	Note
	There is no working card-detect (media change) signal available on the board for the J3 MicroSD slot.

The platform HAL provides definitions to enable access to flash devices on the SPI bus. The HAL enables the QSPI driver (CYGPKG_DEVS_FLASH_QSPI) which in turn provides the underlying implementation for access to the Micron N25Q512A SPI NOR flash. The QSPI support integrates with the CYGPKG_DEVS_FLASH_SPI_M25PXX package. These packages are automatically loaded when configuring for the target. This driver is capable of supporting the JFFS2 filesystem, although at reduced performance compared with a parallel flash device.

In general, devices (Caches, GPIO, UARTs) are initialized only as far as is necessary for eCos to run. Other devices (RTC, SPI, MMC/SD etc.) are not touched unless the appropriate driver is loaded, although in some cases, the HAL boot sequence will set up the appropriate power control and pin multiplexing configuration.

All development and testing was undertaken using the DCT10A22L20G2T4C3ES variant of the Dream Chip Arria 10 SoM and DCT10ABASE Evaluation Baseboard.

Tools

The board support is intended to work with GNU tools configured for an arm-eabi target. The original port was undertaken using arm-eabi-gcc version 7.3.0, arm-eabi-gdb version 8.1, and binutils version 2.30.