| The HAL Port | ||
|---|---|---|
 | Chapter 279. Altera Cyclone V SX Board Support |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the Cyclone V SX hardware, and should be read in conjunction with that specification. The platform HAL package complements the ARM architectural HAL, the Cortex-A variant HAL and the Altera HPS processor HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROM startup, the HAL will perform additional
initialization. This is all done in the
PLATFORM_SETUP1 macro in the assembler header
file hal_platform_setup.h.
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- SDRAM
- This is located at address 0x00000000 of the physical memory space. The HAL configures the MMU to retain the SDRAM at virtual address 0x00000000 with caching enabled. The same memory is also accessible uncached and unbuffered at virtual location 0x40000000 for use by device drivers. The first 1MiB of RAM is left unmapped, allowing NULL pointer accesses to be trapped. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x00100000 to 0x00004000. For ROM startup, all remaining SDRAM is available, although ROM applications actually load from 0x00200000. The virtual vector table is allocated as part of the RedBoot image and occupied 256 bytes from 0x00200050. RAM startup applications are loaded from location 0x00300000, reserving 1MiB for RedBoot.
- On-chip SRAM
- On-chip SRAM is located at 0xFFFF0000 and occupied all of the remaining 64KiB to the top of the address space. It is identity mapped uncached. This port locates the exception vectors to high memory, at 0xFFFF0000. So, the first 32 bytes of SRAM are used for hardware exception vectors and the next 32 bytes are used for the VSR table. SRAM from 0xFFFF0040 is available for application use.
- SPI NOR Flash
- SPI NOR flash media can only be accessed with the Flash API. For the purposes of this API a placeholder address range has been allocated as if the Flash is present at this address. The base of this address range is 0x80000000. This reserved range is not real memory and any attempt to access it directly by the processor other than via the Flash API will result in a memory address exception.
- Peripheral Registers
- These are located at various addresses in the physical memory space above 0xC0000000. When the MMU is enabled, it sets up a direct, uncached, unbuffered mapping so that these registers remain accessible at their physical locations.
SPI NOR Flash
eCos supports QSPI access to the NOR flash on the board. The device is typically used to contain RedBoot and flash configuration data.
Accesses to SPI flash are performed via the Flash API, using 0x80000000 or as the nominal address of the device, although it does not truly exist in the processor address space.
Since SPI flash is not directly addressable, access from RedBoot is only possible using fis command operations.
Real-time characterization
The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built in ARM32 mode.
Example 279.1. cyclone5_sx Real-time characterization
Startup, main thrd : stack used 380 size 1792
Startup : Interrupt stack used 4096 size 4096
Startup : Idlethread stack used 88 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 1 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 1.12 microseconds (22 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 64
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1088
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
0.75 0.55 1.25 0.13 57% 42% Create thread
0.07 0.05 0.25 0.03 98% 57% Yield thread [all suspended]
0.08 0.05 0.30 0.04 78% 67% Suspend [suspended] thread
0.07 0.05 0.15 0.03 62% 62% Resume thread
0.13 0.05 0.70 0.06 75% 71% Set priority
0.01 0.00 0.10 0.02 78% 78% Get priority
0.30 0.20 1.50 0.08 71% 64% Kill [suspended] thread
0.08 0.05 0.15 0.02 65% 32% Yield [no other] thread
0.19 0.15 0.40 0.04 87% 50% Resume [suspended low prio] thread
0.08 0.05 0.30 0.03 93% 60% Resume [runnable low prio] thread
0.11 0.10 0.25 0.02 82% 82% Suspend [runnable] thread
0.07 0.05 0.15 0.03 57% 57% Yield [only low prio] thread
0.06 0.05 0.20 0.02 84% 84% Suspend [runnable->not runnable]
0.27 0.20 0.70 0.05 62% 82% Kill [runnable] thread
0.20 0.15 0.65 0.03 53% 32% Destroy [dead] thread
0.44 0.35 1.10 0.05 81% 68% Destroy [runnable] thread
0.78 0.55 1.90 0.14 59% 26% Resume [high priority] thread
0.26 0.20 0.40 0.04 46% 27% Thread switch
0.00 0.00 0.15 0.00 99% 99% Scheduler lock
0.05 0.00 0.10 0.01 89% 9% Scheduler unlock [0 threads]
0.07 0.05 0.15 0.02 67% 67% Scheduler unlock [1 suspended]
0.08 0.05 0.20 0.02 60% 36% Scheduler unlock [many suspended]
0.08 0.05 0.15 0.02 64% 34% Scheduler unlock [many low prio]
0.03 0.00 0.75 0.05 96% 90% Init mutex
0.09 0.05 0.30 0.04 46% 43% Lock [unlocked] mutex
0.11 0.05 0.60 0.04 68% 25% Unlock [locked] mutex
0.07 0.05 0.40 0.04 93% 75% Trylock [unlocked] mutex
0.05 0.00 0.15 0.01 87% 3% Trylock [locked] mutex
0.02 0.00 0.15 0.03 84% 84% Destroy mutex
0.74 0.65 1.05 0.06 71% 65% Unlock/Lock mutex
0.02 0.00 0.35 0.03 96% 78% Create mbox
0.01 0.00 0.10 0.01 93% 93% Peek [empty] mbox
0.14 0.10 0.85 0.05 93% 93% Put [first] mbox
0.00 0.00 0.00 0.00 100% 100% Peek [1 msg] mbox
0.10 0.05 0.25 0.01 84% 9% Put [second] mbox
0.00 0.00 0.10 0.01 93% 93% Peek [2 msgs] mbox
0.12 0.05 0.75 0.05 84% 9% Get [first] mbox
0.10 0.05 0.25 0.02 87% 6% Get [second] mbox
0.08 0.05 0.30 0.03 50% 46% Tryput [first] mbox
0.09 0.05 0.40 0.05 84% 59% Peek item [non-empty] mbox
0.12 0.05 0.45 0.04 75% 15% Tryget [non-empty] mbox
0.07 0.05 0.20 0.03 62% 62% Peek item [empty] mbox
0.10 0.05 0.30 0.02 68% 25% Tryget [empty] mbox
0.01 0.00 0.15 0.02 84% 84% Waiting to get mbox
0.01 0.00 0.15 0.01 90% 90% Waiting to put mbox
0.03 0.00 0.25 0.04 90% 71% Delete mbox
0.46 0.40 0.90 0.04 68% 25% Put/Get mbox
0.00 0.00 0.15 0.01 96% 96% Init semaphore
0.06 0.05 0.15 0.01 87% 87% Post [0] semaphore
0.10 0.05 0.55 0.04 56% 34% Wait [1] semaphore
0.07 0.05 0.30 0.03 84% 84% Trywait [0] semaphore
0.06 0.05 0.15 0.01 90% 90% Trywait [1] semaphore
0.00 0.00 0.05 0.01 93% 93% Peek semaphore
0.02 0.00 0.20 0.03 87% 87% Destroy semaphore
0.40 0.35 0.85 0.05 34% 46% Post/Wait semaphore
0.02 0.00 0.25 0.03 78% 78% Create counter
0.02 0.00 0.10 0.02 75% 75% Get counter value
0.00 0.00 0.05 0.00 96% 96% Set counter value
0.08 0.05 0.15 0.02 59% 37% Tick counter
0.02 0.00 0.15 0.03 84% 84% Delete counter
0.01 0.00 0.20 0.01 96% 96% Init flag
0.06 0.05 0.40 0.03 90% 90% Destroy flag
0.09 0.05 0.25 0.03 62% 31% Mask bits in flag
0.11 0.05 0.45 0.04 62% 25% Set bits in flag [no waiters]
0.13 0.10 0.65 0.05 93% 84% Wait for flag [AND]
0.12 0.10 0.35 0.03 71% 71% Wait for flag [OR]
0.12 0.10 0.45 0.03 90% 90% Wait for flag [AND/CLR]
0.10 0.05 0.40 0.02 71% 21% Wait for flag [OR/CLR]
0.00 0.00 0.00 0.00 100% 100% Peek on flag
0.05 0.00 0.50 0.03 71% 25% Create alarm
0.12 0.05 0.85 0.06 68% 81% Initialize alarm
0.07 0.00 0.35 0.04 78% 12% Disable alarm
0.11 0.05 0.70 0.04 78% 18% Enable alarm
0.07 0.05 0.20 0.03 71% 71% Delete alarm
0.10 0.05 0.20 0.01 84% 9% Tick counter [1 alarm]
0.46 0.40 0.60 0.03 68% 18% Tick counter [many alarms]
0.16 0.10 0.50 0.03 71% 18% Tick & fire counter [1 alarm]
2.64 2.60 3.15 0.06 90% 90% Tick & fire counters [>1 together]
0.56 0.50 1.10 0.05 50% 90% Tick & fire counters [>1 separately]
0.92 0.90 1.25 0.03 99% 58% Alarm latency [0 threads]
0.98 0.85 1.35 0.06 58% 26% Alarm latency [2 threads]
1.20 1.00 1.65 0.09 51% 14% Alarm latency [many threads]
1.35 1.30 2.15 0.02 79% 18% Alarm -> thread resume latency
0.35 0.35 0.90 0.00 Clock/interrupt latency
0.39 0.30 1.10 0.00 Clock DSR latency
224 172 460 Worker thread stack used (stack size 1088)
All done, main thrd : stack used 1012 size 1792
All done : Interrupt stack used 156 size 4096
All done : Idlethread stack used 232 size 1280
Timing complete - 29810 ms total
PASS:<Basic timing OK>
EXIT:<done>Other Issues
The platform HAL does not affect the implementation of other parts of the eCos HAL specification. The HPS processor HAL and the ARM architectural HAL documentation should be consulted for further details.
| |  | |
| SMP Development and Debugging Support |  | Chapter 280. Dream Chip A10 Board Support |
| 2024-12-10 | eCosPro Non-Commercial Public License |