| The HAL Port | ||
|---|---|---|
 | Chapter 278. Broadcom BCM56150 Reference Board Support |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the BCM56150 Reference hardware, and should be read in conjunction with that specification. The platform HAL package complements the ARM architectural HAL, the Cortex-A variant HAL and the Broadcom IProc processor HAL. It provides functionality which is specific to the target board.
Startup
Following a reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROMRAM startup, the HAL will perform additional
initialization. This is all done in the
PLATFORM_SETUP1 macro in the assembler header
file hal_platform_setup.h.
Linker Scripts and Memory Maps
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- SDRAM
- This is located at address 0x60000000 of the physical memory space. The HAL configures the MMU to retain the SDRAM at virtual address 0x60000000 with caching enabled. The same memory is also accessible uncached at virtual location 0xA0000000 for use by device drivers. The first 128MiB of SDRAM is also mapped to physical address 0x00000000, which is identity mapped uncached. The exception vectors and VSR table occupy the bottom 64 bytes of this region. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x60010000 to 0x60014000. For ROMRAM startup, the application relocates to 0x60100000 and all remaining SDRAM is available. The virtual vector table is allocated as part of the RedBoot image and occupies 256 bytes from 0x60100050. RAM applications load from 0x60200000, reserving 1MiB for RedBoot. JTAG applications load at 0x60100000, overwriting any ROMRAM application already present.
- On-chip SRAM
- On-chip SRAM is located at 0x1B000000 and is 16KiB in size. While this memory is used during DRAM initialization, it is not used by eCos for any other purpose and is available for application use.
- SPI NOR Flash
- SPI NOR flash is supported by a QSPI device that translates read accesses to memory starting at 0x1C000000 into SPI read transactions. Writes to the SPI flash go via a different device which disables this mapping. Because of this, and its poor performance, code should not be executed from SPI flash except during initialization. The Serial flash area at 0x1C000000 is identity mapped uncached, although it should normally be accessed only using the flash API.
- Peripheral Registers
- These are located at various addresses in the physical memory space. When the MMU is enabled, it contain direct, uncached, identity mappings so that these registers remain accessible at their physical locations.
SPI NOR Flash
eCos supports QSPI access to the NOR flash on the board. The device is typically used to contain RedBoot and flash configuration data.
Accesses to SPI flash are performed via the Flash API, using 0x1C000000 as its base address. Access from RedBoot should be made using fis command operations.
Real-time characterization
The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built in ARM32 mode.
Example 278.1. bcm56150_ref Real-time characterization
Startup, main thrd : stack used 388 size 1792
Startup : Interrupt stack used 4096 size 4096
Startup : Idlethread stack used 88 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 1.03 microseconds (1 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 64
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1088
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
INFO:<Ctrl-C disabled until test completion>
1.42 1.00 2.00 0.49 57% 57% Create thread
0.33 0.00 1.00 0.44 67% 67% Yield thread [all suspended]
0.33 0.00 1.00 0.44 67% 67% Suspend [suspended] thread
0.30 0.00 1.00 0.42 70% 70% Resume thread
0.44 0.00 1.00 0.49 56% 56% Set priority
0.16 0.00 1.00 0.26 84% 84% Get priority
0.73 0.00 2.00 0.41 70% 28% Kill [suspended] thread
0.33 0.00 1.00 0.44 67% 67% Yield [no other] thread
0.41 0.00 1.00 0.48 59% 59% Resume [suspended low prio] thread
0.31 0.00 1.00 0.43 68% 68% Resume [runnable low prio] thread
0.36 0.00 1.00 0.46 64% 64% Suspend [runnable] thread
0.33 0.00 1.00 0.44 67% 67% Yield [only low prio] thread
0.31 0.00 1.00 0.43 68% 68% Suspend [runnable->not runnable]
0.67 0.00 1.00 0.44 67% 32% Kill [runnable] thread
0.64 0.00 1.00 0.46 64% 35% Destroy [dead] thread
1.05 1.00 2.00 0.09 95% 95% Destroy [runnable] thread
1.05 1.00 2.00 0.09 95% 95% Resume [high priority] thread
0.42 0.00 1.00 0.49 57% 57% Thread switch
0.14 0.00 1.00 0.24 85% 85% Scheduler lock
0.30 0.00 1.00 0.42 70% 70% Scheduler unlock [0 threads]
0.31 0.00 1.00 0.43 68% 68% Scheduler unlock [1 suspended]
0.32 0.00 1.00 0.44 67% 67% Scheduler unlock [many suspended]
0.30 0.00 1.00 0.42 70% 70% Scheduler unlock [many low prio]
0.19 0.00 1.00 0.30 81% 81% Init mutex
0.25 0.00 1.00 0.38 75% 75% Lock [unlocked] mutex
0.41 0.00 1.00 0.48 59% 59% Unlock [locked] mutex
0.25 0.00 1.00 0.38 75% 75% Trylock [unlocked] mutex
0.28 0.00 1.00 0.40 71% 71% Trylock [locked] mutex
0.09 0.00 1.00 0.17 90% 90% Destroy mutex
1.03 1.00 2.00 0.06 96% 96% Unlock/Lock mutex
0.25 0.00 1.00 0.38 75% 75% Create mbox
0.16 0.00 1.00 0.26 84% 84% Peek [empty] mbox
0.38 0.00 1.00 0.47 62% 62% Put [first] mbox
0.19 0.00 1.00 0.30 81% 81% Peek [1 msg] mbox
0.41 0.00 1.00 0.48 59% 59% Put [second] mbox
0.16 0.00 1.00 0.26 84% 84% Peek [2 msgs] mbox
0.34 0.00 1.00 0.45 65% 65% Get [first] mbox
0.38 0.00 1.00 0.47 62% 62% Get [second] mbox
0.31 0.00 1.00 0.43 68% 68% Tryput [first] mbox
0.28 0.00 1.00 0.40 71% 71% Peek item [non-empty] mbox
0.28 0.00 1.00 0.40 71% 71% Tryget [non-empty] mbox
0.28 0.00 1.00 0.40 71% 71% Peek item [empty] mbox
0.34 0.00 1.00 0.45 65% 65% Tryget [empty] mbox
0.13 0.00 1.00 0.22 87% 87% Waiting to get mbox
0.22 0.00 1.00 0.34 78% 78% Waiting to put mbox
0.19 0.00 1.00 0.30 81% 81% Delete mbox
0.94 0.00 1.00 0.12 93% 6% Put/Get mbox
0.22 0.00 1.00 0.34 78% 78% Init semaphore
0.31 0.00 1.00 0.43 68% 68% Post [0] semaphore
0.34 0.00 1.00 0.45 65% 65% Wait [1] semaphore
0.38 0.00 1.00 0.47 62% 62% Trywait [0] semaphore
0.31 0.00 1.00 0.43 68% 68% Trywait [1] semaphore
0.31 0.00 1.00 0.43 68% 68% Peek semaphore
0.19 0.00 1.00 0.30 81% 81% Destroy semaphore
0.97 0.00 1.00 0.06 96% 3% Post/Wait semaphore
0.25 0.00 1.00 0.38 75% 75% Create counter
0.16 0.00 1.00 0.26 84% 84% Get counter value
0.13 0.00 1.00 0.22 87% 87% Set counter value
0.31 0.00 1.00 0.43 68% 68% Tick counter
0.03 0.00 1.00 0.06 96% 96% Delete counter
0.25 0.00 1.00 0.38 75% 75% Init flag
0.34 0.00 1.00 0.45 65% 65% Destroy flag
0.34 0.00 1.00 0.45 65% 65% Mask bits in flag
0.31 0.00 1.00 0.43 68% 68% Set bits in flag [no waiters]
0.28 0.00 1.00 0.40 71% 71% Wait for flag [AND]
0.31 0.00 1.00 0.43 68% 68% Wait for flag [OR]
0.44 0.00 1.00 0.49 56% 56% Wait for flag [AND/CLR]
0.34 0.00 1.00 0.45 65% 65% Wait for flag [OR/CLR]
0.03 0.00 1.00 0.06 96% 96% Peek on flag
0.28 0.00 1.00 0.40 71% 71% Create alarm
0.44 0.00 1.00 0.49 56% 56% Initialize alarm
0.31 0.00 1.00 0.43 68% 68% Disable alarm
0.41 0.00 1.00 0.48 59% 59% Enable alarm
0.06 0.00 1.00 0.12 93% 93% Delete alarm
0.25 0.00 1.00 0.38 75% 75% Tick counter [1 alarm]
1.28 1.00 2.00 0.40 71% 71% Tick counter [many alarms]
0.47 0.00 1.00 0.50 53% 53% Tick & fire counter [1 alarm]
6.50 6.00 7.00 0.50 100% 50% Tick & fire counters [>1 together]
1.50 1.00 2.00 0.50 100% 50% Tick & fire counters [>1 separately]
1.00 1.00 1.00 0.00 100% 100% Alarm latency [0 threads]
1.00 1.00 1.00 0.00 100% 100% Alarm latency [2 threads]
1.04 1.00 2.00 0.08 96% 96% Alarm latency [many threads]
2.00 2.00 2.00 0.00 100% 100% Alarm -> thread resume latency
0.00 0.00 0.00 0.00 Clock/interrupt latency
1.00 1.00 1.00 0.00 Clock DSR latency
222 164 272 Worker thread stack used (stack size 1088)
All done, main thrd : stack used 812 size 1792
All done : Interrupt stack used 156 size 4096
All done : Idlethread stack used 232 size 1280
Timing complete - 30830 ms total
PASS:<Basic timing OK>
EXIT:<done>Other Issues
The platform HAL does not affect the implementation of other parts of the eCos HAL specification. The IProc processor HAL and the ARM architectural HAL documentation should be consulted for further details.
| |  | |
| Configuration |  | Chapter 279. Altera Cyclone V SX Board Support |
| 2024-12-10 | eCosPro Non-Commercial Public License |