Interrupt Vector Definitions

The file <cyg/hal/hal_platform_ints.h> (located at hal/arm/arm9/at91sam7/VERSION/include/hal_platform_ints.h in the eCos source repository) contains interrupt vector number definitions for use with the eCos kernel and driver interrupt APIs. The exact set of vectors supported depends on the AT91SAM7 model:

For the AT91SAM7S family:

#define CYGNUM_HAL_INTERRUPT_FIQ        0       // Advanced Interrupt Controller (FIQ)
#define CYGNUM_HAL_INTERRUPT_SYS        1       // System Peripheral (debug unit, system timer)
#define CYGNUM_HAL_INTERRUPT_PIOA       2       // Parallel IO Controller A
#define CYGNUM_HAL_INTERRUPT_ADC        4       // Analog-to-Digital Converter
#define CYGNUM_HAL_INTERRUPT_SPI        5       // Serial Peripheral Interface
#define CYGNUM_HAL_INTERRUPT_USART0     6       // USART 0
#define CYGNUM_HAL_INTERRUPT_USART1     7       // USART 1
#define CYGNUM_HAL_INTERRUPT_SSC        8       // Serial Synchronous Controller
#define CYGNUM_HAL_INTERRUPT_TWI        9       // Two-Wire Interface (I2C)
#define CYGNUM_HAL_INTERRUPT_PWMC       10      // PWM Controller
#define CYGNUM_HAL_INTERRUPT_UDP        11      // USB Device Port
#define CYGNUM_HAL_INTERRUPT_TC0        12      // Timer Counter 0
#define CYGNUM_HAL_INTERRUPT_TC1        13      // Timer Counter 1
#define CYGNUM_HAL_INTERRUPT_TC2        14      // Timer Counter 2
#define CYGNUM_HAL_INTERRUPT_IRQ0       30      // External IRQ0
#define CYGNUM_HAL_INTERRUPT_IRQ1       31      // External IRQ0

// Interrupts which are multiplexed on to the System Interrupt
#define CYGNUM_HAL_INTERRUPT_PITC       32      // Period Interval Timer
#define CYGNUM_HAL_INTERRUPT_RTTC       33      // Real-Time Timer
#define CYGNUM_HAL_INTERRUPT_PMC        34      // Power Management Controller
#define CYGNUM_HAL_INTERRUPT_MC         35      // Memory Controller
#define CYGNUM_HAL_INTERRUPT_WDTC       36      // Watchdog
#define CYGNUM_HAL_INTERRUPT_RSTC       37      // Reset Controller
#define CYGNUM_HAL_INTERRUPT_DEBUG      38      // Debug Serial Port

For the AT91SAM7X family:

#define CYGNUM_HAL_INTERRUPT_FIQ        0       // Advanced Interrupt Controller (FIQ)
#define CYGNUM_HAL_INTERRUPT_SYS        1       // System Peripheral (debug unit, system timer)
#define CYGNUM_HAL_INTERRUPT_PIOA       2       // Parallel IO Controller A
#define CYGNUM_HAL_INTERRUPT_PIOB       3       // Parallel IO Controller B
#define CYGNUM_HAL_INTERRUPT_SPI        4       // Serial Peripheral Interface
#define CYGNUM_HAL_INTERRUPT_SPI1       5       // Serial Peripheral Interface 1
#define CYGNUM_HAL_INTERRUPT_USART0     6       // USART 0
#define CYGNUM_HAL_INTERRUPT_USART1     7       // USART 1
#define CYGNUM_HAL_INTERRUPT_SSC        8       // Serial Synchronous Controller
#define CYGNUM_HAL_INTERRUPT_TWI        9       // Two-Wire Interface (I2C)
#define CYGNUM_HAL_INTERRUPT_PWMC       10      // PWM Controller
#define CYGNUM_HAL_INTERRUPT_UDP        11      // USB Device Port
#define CYGNUM_HAL_INTERRUPT_TC0        12      // Timer Counter 0
#define CYGNUM_HAL_INTERRUPT_TC1        13      // Timer Counter 1
#define CYGNUM_HAL_INTERRUPT_TC2        14      // Timer Counter 2
#define CYGNUM_HAL_INTERRUPT_CAN        15      // CAN Controller
#define CYGNUM_HAL_INTERRUPT_EMAC       16      // Ethernet MAC
#define CYGNUM_HAL_INTERRUPT_ADC        17      // Analog-to-Digital Converter
#define CYGNUM_HAL_INTERRUPT_IRQ0       30      // External IRQ0
#define CYGNUM_HAL_INTERRUPT_IRQ1       31      // External IRQ0

// Interrupts which are multiplexed on to the System Interrupt
#define CYGNUM_HAL_INTERRUPT_PITC       32      // Period Interval Timer
#define CYGNUM_HAL_INTERRUPT_RTTC       33      // Real-Time Timer
#define CYGNUM_HAL_INTERRUPT_PMC        34      // Power Management Controller
#define CYGNUM_HAL_INTERRUPT_MC         35      // Memory Controller
#define CYGNUM_HAL_INTERRUPT_WDTC       36      // Watchdog
#define CYGNUM_HAL_INTERRUPT_RSTC       37      // Reset Controller
#define CYGNUM_HAL_INTERRUPT_DEBUG      38      // Debug Serial Port

For the AT91SAM7A3:

#define CYGNUM_HAL_INTERRUPT_FIQ        0       // Advanced Interrupt Controller (FIQ)
#define CYGNUM_HAL_INTERRUPT_SYS        1       // System Peripheral (debug unit, system timer)
#define CYGNUM_HAL_INTERRUPT_PIOA       2       // Parallel IO Controller A
#define CYGNUM_HAL_INTERRUPT_PIOB       3       // Parallel IO Controller B
#define CYGNUM_HAL_INTERRUPT_CAN0       4       // CAN Controller 0
#define CYGNUM_HAL_INTERRUPT_CAN1       5       // CAN Controller 1
#define CYGNUM_HAL_INTERRUPT_USART0     6       // USART 0
#define CYGNUM_HAL_INTERRUPT_USART1     7       // USART 1
#define CYGNUM_HAL_INTERRUPT_USART2     8       // USART 2
#define CYGNUM_HAL_INTERRUPT_MCI        9       // Multimedia Card Interface
#define CYGNUM_HAL_INTERRUPT_TWI        10      // Two-Wire Interface (I2C)
#define CYGNUM_HAL_INTERRUPT_SPI        11      // Serial Parallel Interface 0
#define CYGNUM_HAL_INTERRUPT_SPI1       12      // Serial Parallel Interface 1
#define CYGNUM_HAL_INTERRUPT_SSC0       13      // Serial Synchronous Controller 0
#define CYGNUM_HAL_INTERRUPT_SSC1       14      // Serial Synchronous Controller 1
#define CYGNUM_HAL_INTERRUPT_TC0        15      // Timer Counter 0
#define CYGNUM_HAL_INTERRUPT_TC1        16      // Timer Counter 1
#define CYGNUM_HAL_INTERRUPT_TC2        17      // Timer Counter 2
#define CYGNUM_HAL_INTERRUPT_TC3        18      // Timer Counter 3
#define CYGNUM_HAL_INTERRUPT_TC4        19      // Timer Counter 4
#define CYGNUM_HAL_INTERRUPT_TC5        20      // Timer Counter 5
#define CYGNUM_HAL_INTERRUPT_TC6        21      // Timer Counter 6
#define CYGNUM_HAL_INTERRUPT_TC7        22      // Timer Counter 7
#define CYGNUM_HAL_INTERRUPT_TC8        23      // Timer Counter 8
#define CYGNUM_HAL_INTERRUPT_ADC0       24      // Analog-to-Digital Converter 0
#define CYGNUM_HAL_INTERRUPT_ADC1       25      // Analog-to-Digital Converter 1
#define CYGNUM_HAL_INTERRUPT_PWMC       26      // PWM Controller
#define CYGNUM_HAL_INTERRUPT_UDP        27      // USB Device Port
#define CYGNUM_HAL_INTERRUPT_IRQ0       28      // External Interrupt 0
#define CYGNUM_HAL_INTERRUPT_IRQ1       29      // External Interrupt 1
#define CYGNUM_HAL_INTERRUPT_IRQ2       30      // External Interrupt 2
#define CYGNUM_HAL_INTERRUPT_IRQ3       31      // External Interrupt 3

// Interrupts which are multiplexed on to the System Interrupt
#define CYGNUM_HAL_INTERRUPT_PITC       32      // Period Interval Timer
#define CYGNUM_HAL_INTERRUPT_RTTC       33      // Real-Time Timer
#define CYGNUM_HAL_INTERRUPT_PMC        34      // Power Management Controller
#define CYGNUM_HAL_INTERRUPT_MC         35      // Memory Controller
#define CYGNUM_HAL_INTERRUPT_WDTC       36      // Watchdog
#define CYGNUM_HAL_INTERRUPT_RSTC       37      // Reset Controller
#define CYGNUM_HAL_INTERRUPT_DEBUG      38      // Debug Serial Port

For the AT91SAM7A1 and AT91SAM7A2:

#define CYGNUM_HAL_INTERRUPT_FIQ         0      // Advanced Interrupt Controller (FIQ)
#define CYGNUM_HAL_INTERRUPT_SWIIRQ0     1      // Software Interrupt 0
#define CYGNUM_HAL_INTERRUPT_WD          2      // Watchdog
#define CYGNUM_HAL_INTERRUPT_WT          3      // Watch Timer
#define CYGNUM_HAL_INTERRUPT_USART0      4      // USART 0
#define CYGNUM_HAL_INTERRUPT_USART1      5      // USART 1
#define CYGNUM_HAL_INTERRUPT_CAN3        6      // CAN Controller 3
#define CYGNUM_HAL_INTERRUPT_SPI         7      // Serial Peripheral Interface
#define CYGNUM_HAL_INTERRUPT_CAN1        8      // CAN Controller 1
#define CYGNUM_HAL_INTERRUPT_CAN2        9      // CAN Controller 2
#define CYGNUM_HAL_INTERRUPT_ADC0        10      // Analog-to-Digital Converter 0
#define CYGNUM_HAL_INTERRUPT_ADC1        11      // Analog-to-Digital Converter 1
#define CYGNUM_HAL_INTERRUPT_GPT0CH0     12      // General Purpose Timer 0 Channel 0
#define CYGNUM_HAL_INTERRUPT_GPT0CH1     13      // General Purpose Timer 0 Channel 1
#define CYGNUM_HAL_INTERRUPT_GPT0CH2     14      // General Purpose Timer 0 Channel 2
#define CYGNUM_HAL_INTERRUPT_SWIIRQ1     15      // Software Interrupt 1
#define CYGNUM_HAL_INTERRUPT_SWIIRQ2     16      // Software Interrupt 2
#define CYGNUM_HAL_INTERRUPT_SWIIRQ3     17      // Software Interrupt 3
#define CYGNUM_HAL_INTERRUPT_GPT1CH0     18      // General Purpose Timer 1 Channel 0
#define CYGNUM_HAL_INTERRUPT_PWM         19      // PWM Controller
#define CYGNUM_HAL_INTERRUPT_CAN0        20      // CAN Controller 0
#define CYGNUM_HAL_INTERRUPT_UPIO        21      // Unified Parallel IO Controller
#define CYGNUM_HAL_INTERRUPT_CAPT0       22      // Capture 0
#define CYGNUM_HAL_INTERRUPT_CAPT1       23      // Capture 1
#define CYGNUM_HAL_INTERRUPT_ST0         24      // Simple Timer 0
#define CYGNUM_HAL_INTERRUPT_ST1         25      // Simple Timer 1
#define CYGNUM_HAL_INTERRUPT_SWIIRQ4     26      // Software Interrupt 4
#define CYGNUM_HAL_INTERRUPT_SWIIRQ5     27      // Software Interrupt 5
#define CYGNUM_HAL_INTERRUPT_IRQ0        28      // External Interrupt 0
#define CYGNUM_HAL_INTERRUPT_IRQ1        29      // External Interrupt 1
#define CYGNUM_HAL_INTERRUPT_SWIIRQ6     30      // Software Interrupt 6
#define CYGNUM_HAL_INTERRUPT_SWIIRQ7     31      // Software Interrupt 7