STR7XX — ADC Driver
This driver supports the ADC devices available in some variants of the ST STR7XX family of microprocessors.
The STR7XX ADC produces 12 bit samples. Therefore this driver sets
CYGNUM_IO_ADC_SAMPLE_SIZE to 12. This will cause
the generic layer to define cyg_adc_sample_t as a 16 bit
The ADC hardware is limited to a maximum of 1K samples per channel. Since channels are sampled on a round-robin basis at 4 times this rate, this means that the total sample rate is 4K samples per second.
defines a default sample rate and is initially set to 500.
For each channel X supported the CDL script provides the following configuration options:
- cdl_component CYGPKG_DEVS_ADC_ARM_STR7XX_CHANNELX
- This defines whether the channel is included.
- cdl_option CYGDAT_DEVS_ADC_ARM_STR7XX_CHANNELN_NAME
- This defines the name of the channel.
- cdl_option CYGNUM_DEVS_ADC_ARM_STR7XX_CHANNELX_BUFSIZE
- This defines the size of the channel's sample buffer, in samples.
|2021-04-29||eCosPro Non-Commercial Public License|