NXP — ADC Driver


This driver supports the ADC (Analog-to-Digital Converter) Controller of the NXP i.MX RT microprocessor variants, e.g. the i.MX RT105x family.

Sample Size

The i.MX ADC natively supports 12-bit samples. The controller also supports “low-resolution” 10-bit and 8-bit samples. When higher resolution, averaged, samples are used the maximum achievable sample rate will be lower than the native resolution. The per-controller CYGNUM_DEVS_ADC_NXP_IMX_ADCx_RESOLUTION configuration option specifies the hardware sample resolution to be used.

This driver left-aligns results so that the full-range of the ADC I/O generic layer defined cyg_adc_sample_t type is used regardless of the resolution configured for this driver. The default generic layer CYGNUM_IO_ADC_SAMPLE_SIZE definition of 16 should be sufficient for most applications. However, it should be noted that the underlying cyg_adc_sample_t type is signed, whereas the returned data should be interpreted as an unsigned value (0..MAX) for this controller.


Each ADC device is controlled by a CDL component, CYGHWR_DEVS_ADC_NXP_IMX_ADCx for each controller device x, which must be enabled to initialize the device. The number of channels is currently fixed to 16 for each controller instance, to support the external signals 0..15 as defined by the Processor Reference Manual.

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_RESOLUTION defines the internal hardware sample size.

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_CLOCK allows the selection of the conversion clock as either the internal asynchronous ADACK clock (default) or the system IPG clock. The Processor Reference Manual (PRM) ADC section should be consulted for the pro's and con's of the clock selection, frequency, averaging, etc.

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_SPEED allows the selection of whether the Normal (default) or HighSpeed internal ADACK clock is used.

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_SAMPLE_PERIOD defines the sample period for a conversion as the number of ADC clock cycles.

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_AVG controls whether the hardware averaging is enabled. When enabled the optionCYGNUM_DEVS_ADC_NXP_IMX_ADCx_AVG_SAMPLES specifies the number of samples that are averaged to provide a single reading.

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_OFFSET defines the channel offset compensation applied to all channels..

The option CYGNUM_DEVS_ADC_NXP_IMX_ADCx_DEFAULT_RATE defines the default samples-per-second rate for all channels attached to device x. This default can be over-ridden at run-time using the generic ADC I/O layer provided support as required.

If system instrumentation is enabled then the CYGIMP_DEVS_ADC_NXP_IMC_ADC_INSTRUMENTATION option is made available, and can be enabled to allow the ADC device driver to generate instrumentation. When enabed there are sub-options available to further control which events are recorded.

For each channel x in an ADC device y the CDL script provides the following configuration options:

If the application needs to access the on-chip ADC channel x via an eCos ADC driver then this option should be enabled.
This option controls the name that an eCos application should use to access this device via cyg_io_lookup(), open(), or similar calls. This allows meaningful names to be assigned if required, rather than the default “/dev/adcycx” style.
This defines the size of the channel's sample buffer, in multiples of cyg_adc_sample_t samples.